Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Abstract

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

“…The reference architecture addressed in this work is a processor-coprocessor configuration where the processor runs most of the control flow tasks, while the coprocessor computes the onerous tasks, which in this case are related to the DLS calculation. The processor is the dual core ARM Cortex-A9 present on the addressed ZedBoard, while the coprocessor is fully custom and is generated with the Multi-Dataflow Composer (MDC) tool 3 [39], [40]. Processor and coprocessor communicate through an AMBA AXI4 system bus: the AXI4-Lite protocol is adopted for coprocessor configuration and control purposes, while the AXI4-full one is used for data transfers.…”

StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures

“…The integration of the application-specific hardware blocks has been previously addressed in the context of the high level synthesis (HLS) design flow. Several authors used RVC-CAL language as a single starting point for description of SW and HW components in a heterogeneous platform [47,1,2,51]. Serot et Al [57] developed CAPH programming language for describing and implementing stream-processing applications on reconfigurable hardware, such as FPGAs.…”

Dataflow Modeling for Reconfigurable Signal Processing Systems

“…Two graphs at a time are considered and all the possible mappings are weighted according to the number of sharable connections, then maximum weights drive a certain merging solution. In the RVC-CAL context, Palumbo et al used DPM techniques [46] to create runtime reconfigurable CG substrates, to be used as stand-alone reconfigurable systems [58] or within application-specific accelerators [57]. In those works the combination of the dataflow models and the CG reconfig-urable design paradigm is quite straightforward: each actor is mapped over a single and atomic PE, and multiple input dataflows are combined together over the same substrate adopting a DPM approach.…”

“…This type of reconfigurable architecture is a CG one by definition and the constituting PEs, whose granularity depends on the actors in the given input specifications, are heterogeneous. To facilitate the automatic definition of such an architecture, starting from RVC-CAL DPN input specifications, it is possible to rely on the RVC-CAL compliant design flow presented in [58] -and depicted in Figure 21. In this design flow, an set of tools is adopted to compose, optimize and synthesize the RTL description of the runtime reconfigurable system.…”

“…RVC-CAL compliant reconfigurable architectures, assembled as in [58], can be used as the CG reconfigurable processing core of a co-processing unit, as the one presented in Figure 21 [57]. A DPM-based technique has been used also in a recent work of Edwards et al [19].…”