A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors

Sun, Fei; Ravi, S.; Raghunathan, Anand; Jha, Niraj K.

doi:10.1109/tcad.2007.906457

Cited by 23 publications

(10 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…F. Sun et al [26] proposed a hybrid approach integrating both coprocessors and custom instructions as two different forms of hardware acceleration that can be applicable at different levels of granularity and offer differing trade-offs. This methodology builds upon the basic observations that coprocessors are usually good for coarse-grained tasks and require minimal intervention or support from the processor, while custom instructions are usually suited to fine-grained operations that are best integrated into a processor pipeline.…”

Section: Related Workmentioning

confidence: 99%

CORDIC Hardware Acceleration Using DMA-Based ISA Extension

Manor

Ben-David

Greenberg

2022

JLPEA

View full text Add to dashboard Cite

The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator.

show abstract

Section: Related Workmentioning

confidence: 99%

CORDIC Hardware Acceleration Using DMA-Based ISA Extension

Manor

Ben-David

Greenberg

2022

JLPEA

View full text Add to dashboard Cite

show abstract

“…The proposed approach can be used to rapidly determine if custom instructions should be introduce for fine-grained acceleration in programmable system-on-a-chip alongside with other means of acceleration (e.g. co-processors) [SUN 2007].…”

Section: Our Contributionsmentioning

confidence: 99%

Rapid evaluation of custom instruction selection approaches with FPGA estimation

Lam

Srikanthan

Clarke

2014

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

________________________________________________________________________The main aim of this paper is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in predicting the FPGA performance measures of selected custom instructions. We will present a FPGA estimation technique that partitions the high-level representation of custom instructions into clusters based on the structural organization of the target FPGA, while taking into account general logic synthesis principles adopted by FPGA tools. In this work, we have evaluated a widely-used graph covering algorithm with various heuristics for custom instruction selection. In addition, we present an algorithm called Refined Largest Fit First (RLFF) that relies on a graph covering heuristic to select non-overlapping superset templates, which typically incorporate frequently used basic templates. The initial solution is further refined by considering overlapping templates that were ignored previously to see if their introduction could lead to higher performance. While RLFF provides the most efficient cover compared to the ILP method and other graph covering heuristics, FPGA estimation results reveals that RLFF leads to the worst performance in certain applications. It is therefore a worthy proposition to equip design flows with accurate FPGA estimation in order to rapidly determine the most profitable custom instruction approach for a given application.

show abstract

“…In general, the objective is to determine a Pareto-optimal design with respect to circuit area and delay. For example, a multiobjective evolutionary algorithm [10] based on the Non-dominated Sorting Genetic Algorithm-II (NSGA-II) [11] and a multiobjective simulated annealing algorithm [12] have been proposed for this purpose. Recently, Ando et al proposed an approximate algorithm for the same problem [13].…”

Section: Introductionmentioning

confidence: 99%

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

Kawashima

Zeng

Takase

et al. 2012

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.

show abstract

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors

Cited by 23 publications

References 22 publications

CORDIC Hardware Acceleration Using DMA-Based ISA Extension

CORDIC Hardware Acceleration Using DMA-Based ISA Extension

Rapid evaluation of custom instruction selection approaches with FPGA estimation

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

Contact Info

Product

Resources

About