2007 IEEE International Test Conference 2007
DOI: 10.1109/test.2007.4437587
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Analyzing the risk of timing modeling based on path delay tests.

Abstract: As technology scales, it is becoming increasingly difficult for simulation and timing models to accurately predict silicon timing behavior. When a collection of chips fail in timing in a similar way, diagnosis and silicon debug look to find the root-causes for the failure. However, little work has been done to develop a methodology that looks for useful design information in the good-chip data. This paper describes a path-based methodology that correlates measured path delays from the good chips, to the path d… Show more

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Cited by 16 publications
(11 citation statements)
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“…The methodology was first introduced in [4] with the emphasis on the explanation of the learning algorithm, in particular the Support Vector Machine (SVM) classifier. The features were based on cells and wires and the kernel function used to interpret them was fixed.…”
Section: Introductionmentioning
confidence: 99%
See 4 more Smart Citations
“…The methodology was first introduced in [4] with the emphasis on the explanation of the learning algorithm, in particular the Support Vector Machine (SVM) classifier. The features were based on cells and wires and the kernel function used to interpret them was fixed.…”
Section: Introductionmentioning
confidence: 99%
“…As mentioned in the Introduction, previous works [3,4] focused the study on the learning algorithm, i.e. how and what algorithms should be used for learning and how to rank features.…”
Section: Introductionmentioning
confidence: 99%
See 3 more Smart Citations