Post-Silicon Timing Validation Method Using Path Delay Measurements

Although path-delay faults (PDF) have been studied extensively during the last three decades, design of combinational circuits to achieve low-overhead robust PDF testability, still poses many challenges. In this paper, we revisit the problem of synthesizing a robust path-delay fault testable combinational circuits based on certain new functional properties. Given the boolean cubes of a function, we first design a two-level robust PDF testable circuit by properly grouping the cubes using a few additional control lines. Next, we apply some testabilitypreserving algebraic factorization techniques to design multilevel circuits. The method readily extends to multi-output circuits as well. Experimental results establish that the proposed functional approach yields fully robust PDF-testable circuits with much lower overhead as compared to earlier approaches.

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“…3) Robust Testability By Hybrid Approach Example 7: Consider the 4-variable function f (x1, x2, x3, x4)= (0, 2, 3,4,5,7,8,9,11,14,15). Fig.…”

Section: ) Robust Testability By Using Control Inputsmentioning

confidence: 99%

“…Testing based on path-delay model aims to check whether the delay along a path exceeds the rated clock period, and it has been studied extensively [4], [5], [6], [7], [8], [9], [10], [11], [12]. In order to detect a path-delay fault, a two-pattern test is needed.…”

Section: Introductionmentioning

confidence: 99%

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties

Mitra

Das

Bhattacharya

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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“…If it is possible, integrated circuit manufacturing will benefit at various stages. In post-silicon debug stage, we can validate timing libraries by comparing measured segment delays and the gate or wire delays in the timing model [7]. During manufacturing, we can locate defective segments for faulty chips and perform physical failure analysis, improving yield [5], [6].…”

Section: Introductionmentioning

confidence: 99%

“…However, directly measuring actual segment delays of a chip is not feasible because most internal nodes of the chip are not observable, and intrusive methods are not practical when the number of segments in the chip and its delay impact on functional paths are considered. Thus, many research contributions [5]- [7] have been devoted to obtaining segment delays from path delays, which contain information on the segment delays. This problem is to solve a linear system of equations, but for practical circuits, the system of equations is underdetermined which is usually considered not solvable.…”

Section: Introductionmentioning

confidence: 99%

Segment Delay Learning From Quantized Path Delay Measurements

Chung

Kim

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Our understanding on a silicon chip is limited due to low measurement resolution or model-silicon miscorrelation including variations. This paper shows that chips are better understood by combining noisy measurement results and model information through a mathematical algorithm. Our proposed method learns segment delays in logic circuits from quantized path delay measurements using ridge regression. During the learning process, we take advantage of both nominal segment delays and the delay sensitivity with respect to variations. We also interpret the ridge regression in Bayesian context and in doing so, propose an analytic formula to set the regularization parameter of the ridge regression. For the silicon measurement environments where low measurement resolution is the dominant source of measurement noise, this formula allows us to predict post-silicon results more accurately and speed up the algorithm eliminating inefficient and inaccurate cross-validation. We also demonstrate our method in enhancing the resolution of already measured path delays. We learn segment delays from quantized path delay measurements and predict the path delays prior to the quantization. Our simulation results show that the predicted path delays are much closer to actual values than the measured values and the nominal values.Index Terms-Defect diagnosis, machine learning, post-silicon debug, post-silicon validation.

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“…This is an important problem because a test vector may sensitize several PDFs that lead to the fault output(s). Using the set of measured suspect paths and/or the TF model, techniques as in [4] [5] [6] [7] [8] [11] among many others, address the problem of pruning the set of suspect defective locations. Some of them are designed for fault-diagnosis and others for post-silicon debug [1].…”

Section: Introductionmentioning

confidence: 99%

Identification of delay defects on embedded paths using one current sensor

Aljubouri

Tragoudas

Haniotakis

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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This paper is focused on developing an ATPG-based method that is orthogonal to existing post-silicon debug methods for delay defects. Given an embedded path that contains a small number of gates, the proposed ATPG generates two test vectors so that a current sensor can measure its delay with high accuracy. Unless the cumulative defect along the path is very small, the proposed method will either determine that all locations on it are fault-free or some are defective. This will benefit postsilicon debug methods and, ultimately, failure analysis. No modifications are required in the circuit layout and the routing of the power lines. Experimental results on some of the largest ISCAS85, ISCAS89 and ITC99 benchmarks show that the proposed ATPG tool is capable of generating test vectors which measure the delay of embedded paths that cover on average approximately one fourth of the gates. These results indicate the promise of the method.

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Post-Silicon Timing Validation Method Using Path Delay Measurements

Cited by 9 publications

References 20 publications

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties

Segment Delay Learning From Quantized Path Delay Measurements

Identification of delay defects on embedded paths using one current sensor

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