Analyzing on-chip communication in a MPSoC environment

A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC

“…Currently, designers are increasingly making use of bus-matrix [18] communication architectures to meet the bandwidth requirements of modern MPSoC systems. The need for bus-matrix architectures in high-performance designs and its superiority over hierarchical shared buses has been emphasized in previous work [22]- [24]. Accordingly, we focus on the synthesis of bus-matrix communication architectures.…”

“…Communication architectures have been the focus of much research over the past several years because of their significant impact on system performance [12], [24]. Hierarchical shared bus communication architectures such as those proposed by AMBA [15], CoreConnect [16], and STbus [17] can cost effectively connect few tens of IPs but are not scalable to cope with the demands of modern MPSoC systems.…”

Long-range dependence and on-chip processor traffic

“…In this survey, traffic characterization for NoC performance evaluation is highlighted as a key issue. More specifically related to on-chip traffic generation, two main approaches have been studied: deterministic traffic generation, in which the objective is to exactly reproduce the traffic of a given ip [13,19,20] and stochastic traffic generation which uses random sources in place of real ips [17,25,31]. In the deterministic approach, Mahadevan et al introduced, for instance, a trace compiler able to accurately reproduce the traffic of a processor [20].…”

Performance Analysis of Multimedia Applications using Correlated Streams

“…In [5], a hybrid trace-based simulation methodology was proposed, and in [6] a method that combines the SystemC [7] based MPARM [3] simulation with an analytic technique [8]. Although these mixed methodologies can help to shorten the run-time of simulations, the problem of insufficient corner case coverage is still present.…”

“…Cadence's VCC [2], and academic tools, e.g. MPARM [3] and Ptolemy [4]. These simulation techniques allow the modeling of systems in any level of detail but they often suffer from long run times and from a high set-up effort for each new architecture, mapping and scheduling discipline.…”