Analytically modeling power and performance of a CNN system

Palit, Indranil; Lou, Qiuwen; Acampora, Nicholas; Nahas, Joseph; Niemier, Michael; Hu, Xiaobo Sharon

doi:10.1109/iccad.2015.7372569

Cited by 6 publications

(3 citation statements)

References 23 publications

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“…Power consumption is a related metric to memory use and impacts the usability of implantable devices. Power consumption of neural networks depends on characteristics of the hardware platform on which they are implemented and the energy required to read weights from memory and perform each operation [34]. This study's focus on decreasing the number of weights and FLOPs will have direct impact on decreasing the power consumption of the networks once implemented on a hardware platform.…”

Section: Defining Resource Constraintsmentioning

confidence: 99%

Resource-Efficient Neural Network Architectures for Classifying Nerve Cuff Recordings on Implantable Devices

Hwang,

Genov,

Zariffa

2024

IEEE Trans. Biomed. Eng.

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Background: Closed-loop control of functional electrical stimulation involves using recorded nerve signals to make decisions regarding nerve stimulation in real-time. Surgically implanted devices that can implement this strategy have significant potential to restore natural movement after paralysis. Previous work demonstrated the use of convolutional neural networks (CNNs) to discriminate between activity from different neural pathways recorded by a high-density multi-contact nerve cuff electrode. Despite state-of-the-art performance, that approach required too much data storage, power and computation time for a practical implementation on surgically implanted hardware.Objective: To reduce resource utilization for an implantable implementation, with a minimal performance loss for CNNs that can discriminate between neural pathways in multi-contact nerve cuff electrode recordings.Methods: Neural network (NN) architectures were evaluated on a dataset of rat sciatic nerve recordings previously collected using 56-channel (7 x 8) spiral nerve cuff electrodes to capture spatiotemporal neural activity patterns. The NNs were trained to classify individual, natural compound action potentials (nCAPs) elicited by sensory stimuli. Three architecture types were explored: the previously reported ESCAPE-NET, a fully convolutional network, and a recurrent neural network. Variations of each architecture yielded NNs with a range in the number of weights and required floating-point operations (FLOPs). Each NN was evaluated based on F1-score and resource requirements.Results: NNs were identified that, when compared to ESCAPE-NET, required 1,132-1,787x fewer weights, 389-995x less memory, and 6-11,073x fewer FLOPs, while maintaining macro F1-scores of 0.70-0.71 compared to a baseline of 0.75. Memory requirements range from 22.69 KB to 58.11 KB, falling within the range of on-chip memory sizes from several published deep learning accelerators fabricated in 65nm ASIC technology. Conclusion:Reduced versions of ESCAPE-NET require significantly fewer resources without significant accuracy loss, thus can be more easily incorporated into a surgically implantable device that performs closed-loop real-time responsive neural stimulation.

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Section: Defining Resource Constraintsmentioning

confidence: 99%

Resource-Efficient Neural Network Architectures for Classifying Nerve Cuff Recordings on Implantable Devices

Hwang,

Genov,

Zariffa

2024

IEEE Trans. Biomed. Eng.

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“…We assume a cell similar to that in [22], where a neuron consists of an opamp, a current source, and a threshold function circuit; a synapse consist of 2 operational transconductance amplifiers (OTA), see also [30]. Transistors of various width are used, Table 1.…”

Section: Types Of Neuromorphic Devicesmentioning

confidence: 99%

Benchmarking Delay and Energy of Neural Inference Circuits

Nikonov

Young

2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Numerous neural network circuits and architectures are presently under active research for application to artificial intelligence and machine learning. Their physical performance metrics (area, time, energy) are estimated. Various types of neural networks (artificial, cellular, spiking, and oscillator) are implemented with multiple CMOS and beyond-CMOS (spintronic, ferroelectric, resistive memory) devices. A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across several application cases. Promising architecture/device combinations are identified.In the last few years, AI/ML achieved prominent successes, especially related to deep neural networks (DNN) [7] and convolutional neural networks (CoNN). ML has enabled a revolutionary improvement in the accuracy of image, pattern, and facial recognition, including 2 the treatment of 'big data' online. More demand for neural computing is emerging in robotic control, autonomous vehicles, drones, etc.One of the main concerns on the minds of developers of AI computing systems is the same as for traditional computing: the power consumption in the chips. The history of traditional computing shows that the commercial success of computing devices and architectures is predicated largely on their physical performanceareal density, speed of operation, and consumed energy as benchmarked in [8,9]. These ultimately translate into processing throughput and consumed power of the chips, which are of utmost importance to the user. A fair comparison between the published neural network implementations is difficult due to the difference in the process technology generation, the network architectures, and computing workloads.The main purpose of the paper is to establish a methodology for comparing various neural network hardware approaches and to understand the trends revealed through its development. In doing that we strive to adhere to the following principles: a) general: wide scope of technologies, devices and circuits; b) transparent: simple analytics more important than precise simulations; c) uniform: consistent inputs and assumptions across multiple types of hardware; d) transparent: all models used are described and the code is available [10] to the reader for verification.Let us differentiate this work from the existing body of literature. We do not aim to give a literature review, and refer the reader to the excellent review papers in the neuromorphic hardware field [11,12] which do not attempt to quantitatively compare prior works, as we do in this paper. Oftentimes benchmarking refers to comparing various algorithms for an application mainly based on their accuracy and with little reference to hardware implementation, e.g. [13]. In contrast, we compare different types of hardware implementing the same algorithm and focusing on its energy consumption and performance.The discussion of neural networks in the numerous papers currently being published remains at the architecture level. For example, the accuracy of recognition...

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“…Interconnection between cells is typically local (i.e., nearest neighbor) and space-invariant. For spatio-temporal applications, CeNNs can o er vastly superior performance and power e ciency when compared to conventional von Neumann architectures [47,61]. Using "CeNNs for CoNN" allows the bulk of the computation associated with a CoNN to be performed in the analog domain.…”

Section: Introductionmentioning

confidence: 99%

A Mixed Signal Architecture for Convolutional Neural Networks

Lou

Pan²,

McGuinness

et al. 2019

J. Emerg. Technol. Comput. Syst.

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Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutional neural networks (CoNNs) belong to one of the most popular types of DNN architectures. is paper presents the design and evaluation of an accelerator for CoNNs. e system-level architecture is based on mixed-signal, cellular neural networks (CeNNs). Speci cally, we present (i) the implementation of di erent layers, including convolution, ReLU, and pooling, in a CoNN using CeNN, (ii) modi ed CoNN structures with CeNN-friendly layers to reduce computational overheads typically associated with a CoNN, (iii) a mixed-signal CeNN architecture that performs CoNN computations in the analog and mixed signal domain, and (iv) design space exploration that identi es what CeNN-based algorithm and architectural features fare best compared to existing algorithms and architectures when evaluated over common datasets -MNIST and CIFAR-10. Notably, the proposed approach can lead to 8.7× improvements in energy-delay product (EDP) per digit classi cation for the MNIST dataset at iso-accuracy when compared with the state-of-the-art DNN engine, while our approach could o er 4.3× improvements in EDP when compared to other network implementations for the CIFAR-10 dataset.When considering application-speci c hardware to support neural networks, it is important that said hardware can implement networks that can be extensible to a large class of networks, and solve a large collection of application-level problems. Deep neural networks (DNNs) represent a class of such networks and have demonstrated their strength in applications such as playing the game of Go [54], image and video analysis [32], target tracking [31], etc. In this paper, we use convolutional neural network (CoNN) as a case study for DNNs due to its general prevalence. CoNNs are computationally intensive, which could lead to high latency and energy for inference and even higher latency/energy for training. e focus of this paper is on developing a low energy/delay mixed-signal system based on cellular neural networks (CeNNs) for realizing CoNN.A Cellular Nonlinear/Neural Network (CeNN) is an analog computing architecture [11] that could be well suited for many information processing tasks. In a CeNN, identical processing units (called cells) process analog information in a concurrent manner. Interconnection between cells is typically local (i.e., nearest neighbor) and space-invariant. For spatio-temporal applications, CeNNs can o er vastly superior performance and power e ciency when compared to conventional von Neumann architectures [47,61]. Using "CeNNs for CoNN" allows the bulk of the computation associated with a CoNN to be performed in the analog domain. Sensed information could immediately be processed with no analog-to-digital conversion (ADC). Also, inference-based processing tasks can tolerate lower precision (e.g., Google's TPU employs 8-bit integer matrix multiplies [24]) typically associa...

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Analytically modeling power and performance of a CNN system

Cited by 6 publications

References 23 publications

Resource-Efficient Neural Network Architectures for Classifying Nerve Cuff Recordings on Implantable Devices

Resource-Efficient Neural Network Architectures for Classifying Nerve Cuff Recordings on Implantable Devices

Benchmarking Delay and Energy of Neural Inference Circuits

A Mixed Signal Architecture for Convolutional Neural Networks

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