A Mixed Signal Architecture for Convolutional Neural Networks

Abstract

Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutional neural networks (CoNNs) belong to one of the most popular types of DNN architectures. is paper presents the design and evaluation of an accelerator for CoNNs. e system-level architecture is based on mixed-signal, cellular neural networks (CeNNs). Speci cally, we present (i) the implementation of di erent layers, including convolution, ReLU, and pooling, in a CoNN using CeNN, (ii) modi ed CoNN structures with CeNN-friendly layers to reduce computational overheads typically associated with a CoNN, (iii) a mixed-signal CeNN architecture that performs CoNN computations in the analog and mixed signal domain, and (iv) design space exploration that identi es what CeNN-based algorithm and architectural features fare best compared to existing algorithms and architectures when evaluated over common datasets -MNIST and CIFAR-10. Notably, the proposed approach can lead to 8.7× improvements in energy-delay product (EDP) per digit classi cation for the MNIST dataset at iso-accuracy when compared with the state-of-the-art DNN engine, while our approach could o er 4.3× improvements in EDP when compared to other network implementations for the CIFAR-10 dataset.When considering application-speci c hardware to support neural networks, it is important that said hardware can implement networks that can be extensible to a large class of networks, and solve a large collection of application-level problems. Deep neural networks (DNNs) represent a class of such networks and have demonstrated their strength in applications such as playing the game of Go [54], image and video analysis [32], target tracking [31], etc. In this paper, we use convolutional neural network (CoNN) as a case study for DNNs due to its general prevalence. CoNNs are computationally intensive, which could lead to high latency and energy for inference and even higher latency/energy for training. e focus of this paper is on developing a low energy/delay mixed-signal system based on cellular neural networks (CeNNs) for realizing CoNN.A Cellular Nonlinear/Neural Network (CeNN) is an analog computing architecture [11] that could be well suited for many information processing tasks. In a CeNN, identical processing units (called cells) process analog information in a concurrent manner. Interconnection between cells is typically local (i.e., nearest neighbor) and space-invariant. For spatio-temporal applications, CeNNs can o er vastly superior performance and power e ciency when compared to conventional von Neumann architectures [47,61]. Using "CeNNs for CoNN" allows the bulk of the computation associated with a CoNN to be performed in the analog domain. Sensed information could immediately be processed with no analog-to-digital conversion (ADC). Also, inference-based processing tasks can tolerate lower precision (e.g., Google's TPU employs 8-bit integer matrix multiplies [24]) typically associa...

Benchmarking Delay and Energy of Neural Inference Circuits

“…We follow the treatment of cellular neural networks in [22]. Application of CeNN to CoNN was considered in [42]. Due to both feedback and feedforward connections in a CeNN and due to more connections than just nearest neighbors, the number of synapses is doubled.…”

Energy-Efficient Convolutional Neural Network Based on Cellular Neural Network Using Beyond-CMOS Technologies

“…We show in this section that the core CoNN computation can be readily mapped to a CeNN hardware. In the previous work, the analog implementation of a CeNN-based CoNN has been demonstrated by using CMOS devices to perform energy-efficient non-Boolean computation [30], where the bit precision of the synapse weights is 4. In this section, we describe a few major changes to the activation and pooling layers and apply it to both charge-based analog and spintronic implementation.…”

“…CeNNs are attractive as: 1) each cell is connected to only its neighbors, making the interconnections between cells local and 2) the cells and their synaptic interconnections are usually space-invariant, which makes CeNNs very suitable for CMOS very large scale integration (VLSI) implementation [26]- [29]. CeNN has shown great potential for convolutional neural network (CoNN) type of computations [30], with 8.7× and 4.3× energy-delay product (EDP) improvements compared with the state-of-the-art deep neural network (DNN) acceleration system in MNIST and CIFAR-10 data set, respectively. The CeNN architecture is well suited for the convolution operation, which is the most expensive operation in a typical CoNN.…”

Nonvolatile Spintronic Memory Cells for Neural Networks

“…The dot product has been successfully implemented in hardware in various ways [1]- [4]. Using these dot-product circuits, a cellular neural network (CeNN) accelerator for convolutional neural networks (CoNNs) was designed in [5]. There have been several proposals in recent years for spintronic implementations of CeNNs or CeNNlike structures in hardware, which could be tapped to produce an efficient spintronic CoNN accelerator.…”

“…In this article, we propose to utilize this platform as a hybrid memory/CeNN cell with a high energy efficiency that can be used as analog memory with a built-in activation function. The performance of these cells is simulated in a CeNN-accelerated CoNN performing image classification based on [5]. The spintronic cells significantly reduce the energy and time consumption relative to their charge-based counterparts, needing only ≈ 100 pJ and ≈ 42 ns to compute all but the final fully connected CoNN layer while maintaining high accuracy.…”