Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects

Adan, A.O.; Higashi, K.; Fukushima, Y.

doi:10.1109/16.753707

Cited by 42 publications

(16 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…19,20) As compared to the V th shift of the conventional surface channel ISFET, that of this buried-channel pH sensor (110 mV/pH) is significantly higher than the Nernst limit of 59.5 mV/pH. 21,22) By considering an analytical threshold voltage model and the body potential effect for thin Si SOI devices, 23) the coupling effect of the pH sensitivity can be approximately calculated by…”

Section: Fabrication Of Self-aligned Vertical-channel Poly-simentioning

confidence: 99%

Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal–Oxide–Semiconductor Technology

Chen¹,

Lin²,

Chen³

et al. 2011

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

High-sensitivity polycrystalline silicon (poly-Si) nanowire field-effect transistor (NW FET) pH sensors using top-down and self-aligned fabrication approaches involving the conventional complementary metal-oxide-semiconductor (CMOS) process are reported. For the top-down NW FET, the shrinkage due to reoxidation enables the nanowire width to be scaled to 40 nm without requiring the use of extra lithography equipment, and this improves the electrical uniformity and the performance of the sensors. The surface-ionic coupling operation of this buried-channel field-effect sensor exhibits superior pH sensitivity (threshold voltage shift > 100 mV/pH) as compared to the surface-channel ion-sensitive FET (ISFET). In addition, we report a novel method for fabricating self-aligned, vertical-channel, poly-Si nanowire sensors. The resulting 65-nm self-aligned vertical-channel poly-Si device was found to be feasible for independent-gate bias control, thus enabling its possible integration in very-large-scale integration (VLSI) circuits. Both the abovementioned approaches enable the manufacture of nanowire devices on a large-scale integrated (LSI) circuit using only CMOS manufacturing processes; this provides a high sensitivity, compact and cost-efficient biosensor systems-on-a-chip application. #

show abstract

Section: Fabrication Of Self-aligned Vertical-channel Poly-simentioning

confidence: 99%

Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal–Oxide–Semiconductor Technology

Chen¹,

Lin²,

Chen³

et al. 2011

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…Above all, the steeper subthreshold characteristics make this device suitable for faster switching circuit applications. Although SOI technology is widely used, still some problems like gate transport inefficiency persists …”

Section: Introductionmentioning

confidence: 99%

Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET

Mishra

Bhanja

Mishra

2018

Int J Numerical Modelling

View full text Add to dashboard Cite

This paper attempts to propose a new device as workfunction modulated dual metal rectangular recessed channel silicon on insulator (WMDMRRC-SOI) MOSFET. This model takes the advantage of recessed channel to reduce the hot-carrier effect and a linear variation of workfunction at source side metal gate to achieve improved threshold voltage and electron transportation efficiency. The characteristics of WMDMRRC-SOI MOSFET are analyzed in terms of electron behaviour like mobility, temperature, and velocity in the channel region. The impact of negative junction depth on threshold voltage and short-channel effects like drain induced barrier lowering, subthreshold slope are analyzed to optimize the characteristics of the proposed architecture.Performance parameters of WMDMRRC-SOI MOSFET are compared with the results of DMRRC-SOI MOSFET and conventional RRC-SOI MOSFET.The comparison interprets that with higher intrinsic gain and lower distortion, the proposed architecture gives better analog performance and enhanced short channel parameters. The results obtained are validated through Sentaurus TCAD device simulator. KEYWORDSnegative junction depth (NJD), recessed channel (RC), short-channel effects, silicon-on-insulator (SOI) | INTRODUCTIONScaling of MOS dimensions is essential in order to realize a high-speed and higher-packing density MOS integrated circuit, which results in high power consumption. Attempts to reduce power consumption lead to the degradation of MOSFET carrier transport efficiency. With aggressive technology scaling, the improvement in device reliability has been the prime focus in scaled MOSFET. Thus, performance enhancement can be achieved by overcoming the undesirable short-channel effects. [1][2][3] These barriers can be overcome by silicon-on-insulator (SOI) technology, which is implemented by assimilating an oxide layer on silicon body giving a perfect isolation to avoid latch up in conventional MOS structure. MOSFET along with SOI technology is popular for high temperature applications, as it provides lower leakage current at source/drain junction. Due to its better radiation tolerance, it is also useful for space applications. Above all, the steeper subthreshold characteristics make this device suitable for faster switching circuit applications. Although SOI technology is widely used, still some problems like gate transport inefficiency persists. 4-11

show abstract

“…(5) Using buried oxide layer engineering [53]. (6) Using a graded channel [54] and halo doped SOI structure [55]- [63].…”

Section: Introductionmentioning

confidence: 99%

A review on performance comparison of SOI MOSFET with STS-SOI MOSFET

Karthick

Ajayan

Vivek

et al. 2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

View full text Add to dashboard Cite

The last few decades have seen considerable progress in development of techniques for growing single crystal silicon film on insulator (SOI) substrates suitable for the fabrication of high performance devices. The SOI substrates promise to extend the range of applications including VLSI, memory, analog and digital integrated circuits and mixed signal applications. In this paper, the performance of SOI technology based SOI MOSFETs and schottky tunneling source SOI MOSFETs is reviewed. The SOI technology along with metallic S/D offers several benefits that enable scaling to sub 22nm gate lengths including extremely low S/D parasitic resistances, superior control of leakage current and elimination of bipolar latch up action. STS-FETs also benefits from the use of high-k dielectrics along with S/D engineering and gate engineering. Keywords -Erbium silicide, metal source/drain (S/D), platinum silicide, Schottky barriers (SBs).I.

show abstract

Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects

Cited by 42 publications

References 18 publications

Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal–Oxide–Semiconductor Technology

Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal–Oxide–Semiconductor Technology

Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET

A review on performance comparison of SOI MOSFET with STS-SOI MOSFET

Contact Info

Product

Resources

About