Analytical Models for the Performance of von Neumann Multiplexing

Roelke, George R.; Baldwin, Rusty O.; Bulutoglu, Dursun A.

doi:10.1109/tnano.2006.886737

Cited by 20 publications

(6 citation statements)

References 10 publications

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“…• One possible way to maximize reliability when İ is large and unknown, e.g., time varying [29]- [31], is to rely on "adaptive" gates, so neural-inspiration should play an important role in future nano-scale integrated designs [35]. Finally, precision is very important as "small errors ... have a huge impact in estimating the required level of redundancy for achieving a specified/target reliability" [26]. It seems that current models tend to underestimate reliability at gate-level, and do not do a good job (if at all) at device-level, with Monte Carlo the only widely used method.…”

Section: Discussionmentioning

confidence: 99%

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A fresh look at majority multiplexing when devices get into the picture

Beiu

Ibrahim

Lazarova-Molnar

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

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In this paper we present the first detailed analysis of von Neumann multiplexing (vN-MUX) using majority (MAJ) gates of small fan-ins ǻ (MAJ-ǻ) with respect to the probability of failure of the elementary (nano-)devices. Only gates with small fan-ins have been considered, as gates with large fan-ins do not seem practical (at least in the short term) in future technologies. The extensions from an exact counting algorithm (for gate defects and faults only) to device-level failures will allow us to estimate and characterize MAJ-ǻ vN-MUX with respect to device-level malfunctions. The reported results depart significantly from all known gate-level analyses-either theoretical or based on simulations. These should be quite important as providing a detailed picture of the behavior of MAJ-ǻ vN-MUX when considering the (un)reliability of the elementary (nano-)devices (as opposed to gate-level only analyses). The main conclusion is that small fan-in gates (and redundancy schemes relying on such gates) are quite promising-in spite of all previous results at gate-level showing the contrary.

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Section: Discussionmentioning

confidence: 99%

“…Recently, an analytical model for NAND-2 vN-MUX was also detailed [26]. This one includes other types of faults (e.g., the classical stuck-at faults) besides the classical von Neumann fault (which inverts/flips the output).…”

Section: A Theoretical Analysismentioning

confidence: 99%

A fresh look at majority multiplexing when devices get into the picture

Beiu

Ibrahim

Lazarova-Molnar

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

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“…Reliable block with imperfect decision gate can be evaluated as a series connection of a reliable block with perfect decision gate (14), (15), and an imperfect decision gate (16). Combining (12) and (13) with (15) and (16) gives the final probability of failure of the reliable block as…”

Section: Optimal Redundancy and Cluster Sizingmentioning

confidence: 99%

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Stanisavljević

Schmid

Leblebici

2009

IEEE Trans. Nanotechnology

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This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A faulttolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10 −5 ). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.Index Terms-Fault-tolerant architecture, high defect density, redundancy, reliability of nanoelectronic systems.1536-125X/$25.00

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“…Another aspect is related to the fact that the majority of previous approaches evaluate the reliability of a circuit starting from the gate level and furthermore, most of them rely on the assumption that all gates have the same reliability. However, accurate computation of a circuit reliability at gate-level is of foremost importance, since very small reliability estimation errors at the gate-level can severely impact the reliability evaluation of circuits comprising large numbers of gates [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Probability density function based reliability evaluation of large-scale ICs

Laurenciu¹,

Cotöfană²

2014

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

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For the current advanced technology nodes, an accurate, yet fast reliability analysis is needed at design time, to enable the comparison between different circuit architectures, and thus a reliability-aware design and synthesis process. To this end we propose a reliability assessment framework that is able to estimate more accurately the circuit reliability and which can be applied to large-scale circuit settings, by: (i) taking into account the circuit topology (and implicitly its reconvergent fanouts), the input vectors, the environmental conditions and fault scenarios, (ii) employing a range of probabilities, i.e., a Probability Density Function (PDF), instead of hitherto single probability value, in order to quantify the circuit reliability, (iii) employing variational inference, to derive the circuit primary output PDFs, given its primary inputs PDFs, and (iv) adapting the traditional variational inference approach to exploit the peculiarities of the probabilistic model afferent to logic circuits, for convergence speed improvements and thus applicability in large scale circuits settings.

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Analytical Models for the Performance of von Neumann Multiplexing

Cited by 20 publications

References 10 publications

A fresh look at majority multiplexing when devices get into the picture

A fresh look at majority multiplexing when devices get into the picture

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Probability density function based reliability evaluation of large-scale ICs

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