A fresh look at majority multiplexing when devices get into the picture

Beiu, Valeriu; Ibrahim, Walid; Lazarova-Molnar, Sanja

doi:10.1109/nano.2007.4601325

Cited by 17 publications

(9 citation statements)

References 27 publications

(37 reference statements)

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“…Although a wealth of papers reporting performance analyses of vN-MUX have been published [26]- [34], the analysis in [25] was the first one to consider the devices' probabilities of failure (PFDEV), the gates' topologies, and the input vectors to accurately analyze the performance of vN-MUX schemes. The simulation results reported in [25] have shown that MAJ-3 vN-MUX at RF = 6 outperforms NAND-2 vN-MUX at RF = 9 by a reliability improvement index (RII, see eq.…”

Section: Introductionmentioning

confidence: 99%

On NOR-2 von Neumann multiplexing

Ibrahim

Beiu

Beg

2010

2010 5th International Design and Test Workshop

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This paper provides a detailed analysis of the effects threshold voltage variations play on the reliability of bulk MOSFET transistors. It also investigates the consequences of transistor sizing on the reliability of both devices and CMOS gates. These are followed by very accurate device-level (CMOS technology specific) analyses of NOR-2 von Neumann multiplexing with respect to threshold voltage variations, taking into account both the gates' schematic as well as the input vectors. The simulation results reported here show clearly thatimproving the reliability at the device-level does not necessarily lead to reliability improvement at the gate-and system-level.They also reveal that the effectiveness of von Neumann multiplexing schemes depend to a great extend not only on devices, but also on the gate types (i.e., gates' topologies).

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Section: Introductionmentioning

confidence: 99%

On NOR-2 von Neumann multiplexing

Ibrahim

Beiu

Beg

2010

2010 5th International Design and Test Workshop

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“…Most of the reliability techniques include functional redundancy. Common techniques include R-fold modular redundancy (RMR), including triple modular redundancy (TMR) as the most common implementation [3], [4]- [6], cascaded TMR (CTMR) [3], [7], different multiplexing schemes [4], [8]- [16], and reconfiguration [17]- [20]. Each of these techniques has an optimal space of application, depending on defect density, type of defects, and size of a chip.…”

Section: Introductionmentioning

confidence: 99%

“…Techniques like RMR and CTMR require very coarse granularity level (10 6 -10 7 devices in a redundant unit) and low device failure probability (10 −8 -10 −7 ) [3], [7]. On the other hand, techniques like NAND/MAJ multiplexing could be efficient at finer granularity levels and higher device failure probability, requiring moderate redundancy factors (10-100) [11]- [16]. Reconfiguration offers good performance in terms of tolerable defect density and granularity level, but cannot correct transient errors and needs long testing/configuration time [3], [11], [20].…”

Section: Introductionmentioning

confidence: 99%

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Stanisavljević

Schmid

Leblebici

2009

IEEE Trans. Nanotechnology

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This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A faulttolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10 −5 ). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.Index Terms-Fault-tolerant architecture, high defect density, redundancy, reliability of nanoelectronic systems.1536-125X/$25.00

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“…The RMR technique requires a very coarse granularity level (10 6 to 10 7 devices in a redundant unit [6]) and low device failure probability (10 −8 to 10 −7 ) [2]. On the other hand, techniques like NAND/MAJ multiplexing could be efficient at finer granularity levels and higher device failure probability, requiring moderate redundancy factors (10-100) [7], [9]. Reconfiguration offers the best performance in terms of tolerable defect density and granularity level, but cannot correct transient errors and needs long testing/configuration time [2], [7].…”

Section: Introductionmentioning

confidence: 99%

“…Finally, taking (8) into consideration, it becomes clear that P block f ails, (2) from (11) is negligible compared to P block f ails from (9). Since the joint probabilities for reliable blocks are negligible, the chip fails if any of the outputs of any reliable block fails; hence, the upper bound probability that the whole chip fails is…”

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confidence: 99%

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

Stanisavljević

Schmid

Leblebici

2009

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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The theoretical analysis of R-fold modular redundancy with distributed voters -distributed R-fold modular redundancy, in terms of reliability is presented for the first time to the best of author's knowledge. This technique is compared in terms of resistance to massive levels of defect density expected in future nano-devices to R-fold modular redundancy with a single voter, cascaded R-fold modular redundancy and NAND multiplexing. Optimal partition size analysis and redundancy optimization of distributed R-fold modular redundancy technique has been performed for the first time in the context of a large-scale system. The optimal window of application of different fault-tolerant techniques with respect to defect density is presented as a way to find the optimum design trade-off between the reliability and power/area.

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A fresh look at majority multiplexing when devices get into the picture

Cited by 17 publications

References 27 publications

On NOR-2 von Neumann multiplexing

On NOR-2 von Neumann multiplexing

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

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