Analytical modeling of the SOI four-gate transistor using conformal mapping

Snigdha, Farjana; Bappy, Mehedy Hasan; Sultana, Nasrin; Shuvra, S. R.; Chowdhury, Tasmin; Khan, Md. Ziaur Rahman

doi:10.1109/icece.2012.6471673

Cited by 2 publications

(1 citation statement)

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“…S. Jahangir et al [14], [15] have shown a numerical model which was developed to obtain the potential distribution [16], [17] solving 2-D Poisson equation in Depletion-All-Around (DAA) operation of n-channel Silicon-On-Insulator (SOI) G 4 -FET. Ballistic current-voltage model in DAA was also shown in [18]. In this paper, Graphene which has lower relative permittivity and very higher mobility than Silicon is used as the channel of G 4 -FET and GAA MOSFET to increase the potential distribution and drain current.…”

Section: Introductionmentioning

confidence: 99%

Drain Current Model of Graphene Channel G 4 -FET and Gate-All-Around MOSFET

Alam¹,

Pathan²,

Rahman³

2018

International Journal of Innovative Research in Electrical, Ele

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Potential distribution and Wave function distribution are obtained by solving 2-D Poisson-Schrödinger equation using COMSOL with MATLAB. Conduction band profile and carrier density are investigated. Drain current of Graphene Channel Four Gate Transistor (G 4 -FET) and Gate-All-Around (GAA) MOSFET are calculated and compared. CONCLUSIONThe potential distribution and Wave function distribution for n-Graphene channel G 4 -FET and GAA MOSFET have been obtained by solving 2-D Poisson-Schrödinger equation using COMSOL with MATLAB. The maximum potential of G 4 -FET and GAA MOSFET has been compared. Conduction band profile and carrier density has been investigated. Drain current of n-Graphene channel G 4 -FET and GAA MOSFET has been calculated and compared with n-Silicon channel G 4 -FET. In the future, transconductance, threshold voltage, Sub-threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), on-off current ratio will be calculated for those structures.

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