Analytical Modeling of Surrounding Gate Junctionless MOSFET Using Finite Differentiation Method

Preethi, S.; Balamurugan, N. B.

doi:10.1007/s12633-020-00653-5

Cited by 16 publications

(3 citation statements)

References 19 publications

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“…For modeling, parabolic approximation method was used to model different types of TFETs like single gate silicon-on-insulator (SOISG) TFET, dual material double gate TFET [12], and dual material gate work function engineered surrounding gate TFET [13]. Next, Kane's model and the 2D poisson equation togetherly used to model surrounding gate tunnel FET and reported effects of stacked oxide and double metal gates on subthreshold swing, drain current, and electric fields [14].…”

Section: Introductionmentioning

confidence: 99%

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

Chaudhary,

Dewan,

Singh

et al. 2024

Eng. Res. Express

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Here, an explicit analytical model of electrical properties like channel potential, electric field, drain current, and threshold voltage for a negative capacitance DGTFET structure is developed. The model properly calculates the channel potential profile by solving the Poisson equation using the Landau-Khalatnikov (LK) model (for incorporating the NC effect). The electric field expression is developed using a channel potential model. The drain current expression is obtained by mathematically integrating the rate of band-to-band tunneling generation over the channel thickness. The threshold voltage has been derived using a method called maximal trans-conductance. Furthermore, by varying the FE parameters like thickness (tfe), coercive field (EC), and residual polarization (PR), we improve capacitance matching and gate control of the device. All of the model results demonstrated a perfect alignment with those discovered by TCAD simulations. Designing devices and circuits for low-power applications can be more effective from these results.

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Section: Introductionmentioning

confidence: 99%

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

Chaudhary,

Dewan,

Singh

et al. 2024

Eng. Res. Express

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“…Chattopadhyay et al 72 proposed a comprehensive analytical model for linearity, non-linearity & intermodulation distortion for rectangular GAAJLFET utilising three-dimensional surface potential & drain current. The author has compared the modeling data with simulation results for validation.…”

mentioning

confidence: 99%

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Raut¹,

Nanda²,

Panda³

2023

ECS J. Solid State Sci. Technol.

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Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

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“…Gate stack consist of low and high dielectric constant materials. 5,6 The device presented in this paper can become a milestone in the semiconductor Industry.…”

mentioning

confidence: 99%

Performance Investigation of a Dielectric Stacked Triple Material Cylindrical Gate All Around MOSFET (DSTMCGAA) for Low Power Applications

Gupta¹,

Gupta²,

Gupta³

et al. 2023

ECS J. Solid State Sci. Technol.

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This paper presents an analysis of gate stacked triple material dual-halo cylindrical MOSFET. The surface potential and electric field have been plotted for the proposed device using TCAD Silvaco at various channel lengths. The analytical model of surface potential, field and subthreshold current is also present. A comparative analysis has been accomplished for the proposed device with Asymmetric gate stack triple metal gate all around (AGSTMGAA), dual dielectric triple metal surrounding gate (DDTMSG) and Triple metal surrounding gate MOSFET. The performance metric of the device has been investigated in terms of Drain Induced Barrier Lowering (DIBL), Subthreshold swing and threshold-voltage roll-off. Furthermore, the analog behaviour of the device has been evaluated by determining transconductance, early voltage and intrinsic gain. The proposed device shows much better performance when compared to its counterpart. The mitigation in DIBL and leakage current indicates the cut back in the SCEs. The proposed device shows 8% improvement in SS, 36.2% improvement in DIBL and 13.5% improvement in threshold voltage roll-off as compared to AGSTMGAA. Hence, it can be used for low power applications.

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Analytical Modeling of Surrounding Gate Junctionless MOSFET Using Finite Differentiation Method

Cited by 16 publications

References 19 publications

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

A physics based model for negative capacitance TFET considering variation in ferroelectric parameters

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Performance Investigation of a Dielectric Stacked Triple Material Cylindrical Gate All Around MOSFET (DSTMCGAA) for Low Power Applications

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