Analysis of trap and recovery characteristics based on low-frequency noise for E-mode GaN HEMTs with p-GaN gate under repetitive short-circuit stress

Xu, X. B.; Li, B; Chen, Y Q; Wu, Zhaohui; He, Zhiyuan; En, Yunfei; Huang, Yun

doi:10.1088/1361-6463/ab713a

Cited by 6 publications

(4 citation statements)

References 25 publications

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“…Based on literature, three mechanisms apply during stress but not to the same extent. First charge trapping under gate electrode is responsible for threshold voltage shift [6].…”

Section: Resultsmentioning

confidence: 99%

Degradation of 600V GaN HEMTs under Repetitive Short Circuit Conditions

Marek¹,

Kozarik²,

Chvála³

et al. 2021

ISPS'21 Proceedings

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This paper descirbes impact of repetitive short-circuit stress on commercially available 600V e-mode GaN HEMTs with p-GaN gate. The devices were subjected to up to 10 5 short circuit stress cycles at 100V and 300V drain voltage. Tests at voltages over 300V resulted in destruction of the devices. Electrical characteristics were measured prior to, and after each sequence of pulses to observe gradual effects of repetitive SC stress. The devices were also analysed by DLTS. A shift in all of the measured characteristics was observed. Amount of the shift does not correlate with the number of SC cycles, which suggests more parameters of the devices are affected. The shifts were also more pronounced at higher drain voltage. The trapping was also analysed using DLTS. Due to high complexity of the spectra, only the traps verified by simulation were investigated. At 100V stress voltage, the shift in DLTS spectra was small, at 200V it was significant. Full analysis of possible origin of the observed deep levels is still ongoing.

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“…Based on literature, three mechanisms apply during stress but not to the same extent. First charge trapping under gate electrode is responsible for threshold voltage shift [6].…”

Section: Resultsmentioning

confidence: 99%

Degradation of 600V GaN HEMTs under Repetitive Short Circuit Conditions

Marek¹,

Kozarik²,

Chvála³

et al. 2021

ISPS'21 Proceedings

View full text Add to dashboard Cite

show abstract

“…Based on literature, three mechanisms apply during stress but not to the same extent. First charge trapping under gate electrode is responsible for threshold voltage shift [6]. Trapping in drain access region causes decrease of free charge in the 2DEG [7] and both trapping effects are decreasing mobility of carriers in the 2DEG [8] affecting on-resistance and saturation current.…”

Section: Resultsmentioning

confidence: 99%

Degradation of 600V GaN HEMTs under Repetitive Short Circuit Conditions

Kozarik

Marek

Minárik

et al. 2020

2020 13th International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM)

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“…This pulsed negative V GS bias stress modulates the negatively charged trap density with an increase in V GS bias stress and increase in stress pulse (t stress ). However, the p-GaN gate HEMT device structure has no oxide layer compared with the MIS-HEMT device, which tells us that the reported surface state trapping mechanisms with oxide layer are not applicable here, although some research on the reliability of commercialized E-mode GaN HEMT with p-GaN gate under reverse electrostatic discharge stress and repetitive short circuit stress has reported that the degradation mechanism could be addressed by the formation of traps at the barrier layer, p-GaN/AlGaN hetero-interface, and AlGaN/GaN interface [26,27]. At the present work, we studied the degradation behavior and mechanism for the impact of various negative gate stress voltage pulses without drain stress bias at room temperature.…”

Section: Gate-lag Effectmentioning

confidence: 91%

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

2021

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In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

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Analysis of trap and recovery characteristics based on low-frequency noise for E-mode GaN HEMTs with p-GaN gate under repetitive short-circuit stress

Cited by 6 publications

References 25 publications

Degradation of 600V GaN HEMTs under Repetitive Short Circuit Conditions

Degradation of 600V GaN HEMTs under Repetitive Short Circuit Conditions

Degradation of 600V GaN HEMTs under Repetitive Short Circuit Conditions

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

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