Analysis of timing jitter in CMOS ring oscillators

Abstract

In this paper the erects of thennul noise in transistors on riming jitter in CMOS ring-oscillators composed of sourre-coupled differential resistively-louded deluy celLs is investigated. The mlutionship between deluy element design parameters und the inherent thermal noise-induced jitter of the generated wavefonn are unulyzed These results ure compared with simuhed results from U Monte-curlo analysis with good ugreemenr. The unulysk shows that timing jitter is inversely proportional to the squure root of the total capacitance at the output of euch inverter; und inversely proportional to the gate-source bias voltage ubove threshold of the sourre-coupled devices in the bulunced state. Furthermore, these dependencies imply an inverse nzlationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter pe@ormance are predicted to improve ut a rute of IO dB per decade increuse in power consumption. I . IntroductionRing oscillators are widely used in phase-locked-loops (PLL) for clock and data recovery, frequency synthesis, clock synchronization in microprocessors, and many applications which require multi-phase sampling [l] [2]. In many such applications, clock signals are generated to drive mixers or sampling circuits in which the random variation of the sampling instant, or jitter, is a critical performance parameter. In some applications the frequency domain equivalent of jitter, called phase noise, is important. A block diagram of a typical PLL using a ring-oscillator for multi-phase clock generation is shown in figure 1. Jitter requirements in typical applications range from on the order of 100 picoseconds r.m.s. down to less than 5 picoseconds in very high-speed communications receivers, for example.Jitter can arise from many sources, including inadvertent injection of signals from other parts of the circuit through the power supply. However, interfering sources like these can often be minimized by the use of circuit techniques such as differential implementations. In a fully optimized design the main source of timing jitter is the inherent thermal andor shot noise of the active and passive devices that make up the inverter cell. l/f noise is usually not of practical importance since it is rejected by the PLL loop filter, and does not effect the stage-to-stage delay in a DLL. Therefore minimizing the impacts of thermal and shot noise in the basic inverter cells hecomes the key to attaining low timing jitter. 1. Research supported by NSF, ARPA, and the California MICRO Program Figure 1. Ring-oscillator phase-locked-loop with multiphase samplingThis paper attempts to determine analytically and through simulation the relationship between the design parameters of the inverter cell used in the ring-oscillator and the resulting noise-induced jitter. The class of circuits analyzed is source-coupled differential delay cells with resistive loads, implemented in CMOS technology, where the loads are realized by PMOS transistors in the triode region (figure 2). This pa...

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

“…The last form of the equation is obtained using the square law model for the transistor current. In [183] an analysis of a differential delay cell yielded similar results. Probably the main finding in this jitter equation is its dependence on inverter DC gain (g m r o ), which is due to the fact that at low frequencies the noise current is transformed into voltage in the output resistance.…”

A Slew Controlled LVDS Output Driver Circuit in 0.18 $\mu$m CMOS Technology

“…Therefore, because of smaller voltage slew at the input of , the total jitter due to this element at the output will increase [12]. Hence, the values of and in Fig.…”

“…11(a), the total current consumption of the circuit can be calculated by (11) Here, is the total bias current of the predriver stage which is implemented by a two stage SCL-based buffer [as shown in Fig. 2(a)], and is the bias current of the output LVDS driver: (12) It can be shown that is proportional to the as well as to the voltage swing at the input of LVDS stage called (as depicted in Fig. 11(a)).…”

Analysis and Equalization of Data-Dependent Jitter

“…Therefore, a design tradeoff exists between compensating DDJ and introducing additional random jitter. From [5], the random jitter introduced through a CMOS buffer stage is (32) where is the load capacitance, is the stage bias current, and is a bias dependent term. The delay of the stage, if slew rate limited as in our cross-coupled stages, is where is the logic swing.…”

“…RJ results from the translation of random voltage noise into timing fluctuations due to buffering [5] or phase noise of the transmitter and receiver [6], [7]. On the other hand, DJ has distinct circuit origins and is correlated to limited bandwidth, signal reflection, duty cycle distortion, or power supply noise [8].…”