Analysis of Static and Dynamic Performance of Short-Channel Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors for Improved Cutoff Frequency

Abstract

The quantum efficiency and lifetime of fluorescence of an aluminum-hydroxyquinoline (Alq 3 ) complex in solution increased with decreasing polarity of the solvent. Similarly, the fluorescence quantum efficiency and lifetime of Alq 3 films were increased by mixing the complex with a compound with a low dielectric constant. These results suggested that the nonradiative decay process of Alq 3 is retarded in less polar media. The quantum efficiency and lifetime of fluorescence of Alq 3 films were 20 AE 2% and 17 ns, respectively. When Alq 3 was mixed with a less polar substance in the film state, the quantum efficiency and lifetime were increased to 25 AE 2% and 20 ns, respectively. These results indicate that the nonradiative decay process in the film state is also retarded as the polarity decreases. Using a film consisting of Alq 3 and a compound with a low dielectric constant as the light emitting layer of organic electroluminescence devices, the luminance efficiency was increased by about 20%.

High Tolerance to Gate Misalignment in Low Voltage Gate-Underlap Double Gate MOSFETs

“…OUBLE GATE (DG) MOSFET has received considerable attention in recent years owing to the inherent suppression of short channel effects (SCEs), volume-inversion effect and excellent scalability [1], [2]. DG MOSFETs fabricated with channel in the plane of the wafer (standard configuration) [3], pose the difficult problem of how to fabricate a bottom gate underneath the FET body and align it to the top gate.…”

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

“…8) which implies an increased g m at the same current. Multigate devices (FinFETs) achieve higher values of g m than single gate devices at lower V gs due to the volume inversion effect [3]. Also, it is important to note that SDE devices designed with larger σ (≥ 12.5 nm) along with wider spacers (≥ 60 nm) result in the degradation of g m (and f T ) due to parasitic series resistance effect.…”

“…While digital system design has continually pushed for the increased speed of minimum size devices, analog designers have often employed longer channels to avoid shortchannel effects (SCEs) and achieve higher voltage gain. However, in the nanoscale regime, upcoming CMOS technologies face many technological challenges [1], the most crucial being the SCEs that tend to degrade the analog figures of merit (FOM) such as Early voltage (V EA ), transconductance-to-current ratio (g m /I ds ), intrinsic dc gain (A VO = g m /g ds = g m /I ds × V EA ) and cutoff frequency (f T = g m /2πC gg where g m is the transconductance and C gg is the total gate capacitance) [2], [3]. To overcome the degradation in analog FOM, certain techniques such as HALO implants and laterally asymmetric channel (LAC) or graded-channel (GC) design [4], [5] have been proposed.…”

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

“…An improvement in g m (as compared with abrupt SDE devices) of 10% and 28% (independent of s s /L g ) with d = 5 and 9 nm/dec, respectively, is attained at s d /L g = 2. DG devices achieve higher values of g m than single gate devices at lower gate biases due to the volume inversion effect [26]. The most significant aspect of asymmetric SDE regions is the reduction in g ds with an increase in s d /L g .…”