Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates

Abstract

IntroductionThe floating body RAM is a very promising candidate for further downscaling of memory cells [1,2]. Amongst the different SOI-based device architectures, Ultra-Thin BOX (UTBOX) SOI devices have gained a lot of interest recently [3]. As the buried oxide (BOX) thickness is scaled down, a low-voltage back bias can be used to increase the sense margin. In this work, we will first discuss the impact of back biasing on the sense margin in both doped and undoped devices. As the floating body memory cell requires the use of impact ionization or Gate Induced Drain Leakage (GIDL) [4] to program state "1", reliability is a concern. Therefore, the second part of this paper will be devoted to the reliability study.Device fabrication The nMOSFETs are fabricated on a SOI substrate with 10nm BOX and 30nm Si film. The gate stack consists of 5nm PE-ALD TiN, capped with 100nm poly-Si, on 5nm SiO 2 . A standard flow is used for the rest of the processing. Fig. 1 shows a schematic view of the process flow and device under investigation.Discussion A. Impact of back bias The applied bias conditions are shown in Fig.2. GIDL programming is used to write "1" and forward biasing of the body-drain junction is used for state "0". The sense margin ΔI S is defined as the difference in source current between "1" and "0" after a hold time t HOLD =50µs. Fig.3. shows the sensitivity of the threshold voltage to the back bias V BS for devices with doped (N SUB~1 e18 cm -3 ) and undoped channels. The strong coupling between front and back gate in undoped devices leads to a high dependence of V T on V BS . This sensitivity is reduced for doped channels. However, Fig.4 shows that back biasing is still interesting for doped channels. State "1" is stable over the entire range of V BS indicating that the back interface is in accumulation and a large amount of holes are stored. It is confirmed by Fig.5 that the generation of electron-hole pairs through GIDL is little impacted by V BS . As V BS becomes more positive, a small degradation of "1" can be seen as the holes are recombining with the attracted electrons. Fig. 4 shows that state "0" can be largely dependent on V BS indicating that ΔI S and retention are mainly defined by the efficiency in removing holes (or attracting electrons) from the body. As V BS is negative, the back interface is in accumulation and holes are attracted thereby degrading "0". Making the V BS more positive, the back interface moves from depletion to inversion and electrons are attracted to the back interface. In this case, the use of positive V BS is beneficial. The V BS -dependence for undoped channels is different (Fig. 6). The front potential is directly impacted by V BS through the front-back gate coupling. At positive V BS , state "1" is constant as the width of the accumulation layer at

Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results

“…The structure simulated in this work (UTBOX SOI) was based on the process information of reference [10]. The gate stack is composed of 5nm of SiO 2 under a TiN electrode.…”

“…However, the second generation of those devices uses the parasitic BJT in a positive feedback loop, thereby greatly improving retention times and sense margins [11]. In every SOI structure, and especially in decananometer devices, a parasitic bipolar transistor is always present [10] as illustrated in Figure 5.…”

One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect

“…Since a high drain bias results in damage to the device due to the impact ionization and other high electric field effects, it forms a limiting factor for good FBRAM (Floating Body Random Access Memory) operation limiting the reliability [3,8]. On the other hand, a low drain voltage is not sufficient to trigger the BJT effect [9].…”

Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs

“…A p-type ground plane (GP) implantation was done which is considered as a back gate. More process information can be found in [9]. III.…”