Analysis of Power Consumption Sar-Adc Dynamic Comparator

Abstract

Due to the high demand of ultra-low power in digital application, the needs of energy efficient analog-to-digital converter (ADC) are really essential. The comparator being an important part of successive approximation register (SAR)-ADC needs to have optimum performance under low power condition. This paper presents the comparison on power consumption together with the output performance flow power SAR-ADC dynamic comparators from three different design proposed by previous researchers. The three circuits is simulated and compared in terms of power consumption, regeneration time, reset time and output transient. The simulation is using Cadence Spectre and setup with 0.18µm CMOS technology, VDD at 0.8V and clock speed 2 at MHz. The analysis results obtained provides the lowest voltage input different (ΔVin) possible for double tail dynamic comparator using 0.18µm CMOS technology while adhering to the 45 corner process requirement. The results can be used as references for further design of ultra-low power dynamic comparator.

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

“…The comparator passes all 45 process corner in clock frequency 2MHz. As shown in Figure 6, the proposed design able to operate in For process corner (FS;720mV;0°C), failure occurred in test sequence number (3,6,8,9,11). The failure occurred in minimum positive input INP is 400.4mV.…”

“…To ensure the robustness of a design, process corner simulation is required at the design stage. Process corner represents the extremes parameter variation of integrated circuit design which is fabricated on semiconductor wafer [6][7][8][9][10][11][12][13][14][15]. Parameter variations include range of process transistor properties, supply voltages and die temperatures [8,9].…”

“…In nanoscale technology, scaling down of voltage supply near to threshold voltage can provide excessive savings in dynamic energy. However it will reduce the voltage headroom for cascode structure to operate correctly [7][8][9][10][11][12][13][14][15][16][17]. Therefore, to design low voltage and low power dynamic comparator with low supply voltage is a big challenge when the number of transistor stacking is high [16][17][18][19][20][21][22][23].…”

“…The most popular energy efficient comparator is dynamic comparator Figure 1 which only operates during regeneration time [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The additional features are high input impedance, rail to rail output swing, zero static power, low offset voltage and fast decision making that comes from strong positive feedback and .…”