Analysis of power consumption on switch fabrics in network routers

Ye, Terry Tao; Micheli, Giovanni De; Benini, Luca

doi:10.1145/513918.514051

Cited by 198 publications

(65 citation statements)

References 9 publications

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“…We again make a first order approximation of the power consumption for the model. Based on the results presented in References [23] and [24], this is a good approximation for network elements:…”

Section: Cpumentioning

confidence: 98%

Power efficiency of thin clients

Vereecken

Deboosere

Simoens

et al. 2010

Trans Emerging Tel Tech

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Abstract-Thin client computing trades local processing for network bandwidth consumption by offloading application logic to remote servers. User input and display updates are exchanged between client and server through a thin client protocol. This thin client protocol traffic can lead to a significantly higher power consumption of the radio interface of the wireless device. In this contribution, we present a cross-layer algorithm that exploits thin client protocol layer information to determine intervals where no traffic from the server is expected. During these intervals, the wireless network interface card (WNIC) is instructed to enter the energy conserving sleep mode. Using this algorithm for a remote text editor, WNIC energy consumption reductions of 21-52 % can be achieved.

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Section: Cpumentioning

confidence: 98%

Power efficiency of thin clients

Vereecken

Deboosere

Simoens

et al. 2010

Trans Emerging Tel Tech

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“…The flits from the source node need to traverse multiple hops consisting of routers and wires to reach destinations. Thus, energy consumption increases with the number of hops required by the flits to traverse from the source to the destination [21]. The proposed XDMesh reduces the average number of hops and energy consumption in the network by inserting diagonal links.…”

Section: Packethop I Refersmentioning

confidence: 99%

An Extended Diagonal Mesh Topology for Network-on-Chip Architectures

Furhad

Kim

2015

IJMUE

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This paper proposes an extended diagonal mesh (XDMesh) topology for network-onchip (NoC) architectures to reduce latency and energy consumption for fast and lowpower communication among remote nodes by including diagonal links in the network. In addition, we compare the performance of the proposed XDMesh with conventional stateof-the art topologies, including mesh, extended-butterfly fat tree (EFTI), and diametrical mesh, in terms of throughput, latency, energy consumption, and area overhead. Experimental results indicate that XDMesh outperforms the conventional topologies in terms of throughput and latency by varying the number of virtual channels and injection rate. Moreover, XDMesh achieves 46.28%, 35.29% and 19.37% lower energy consumption than EFTI, mesh, and diametrical mesh topologies, respectively, and 9.29%, 31.28%, and 15.23% lower silicon area, respectively. 198Copyright ⓒ 2015 SERSC throughput, high bandwidth, reusability, and lower power consumption for communication can be achieved with NoC-based architectures [6].A number of topologies have been proposed in previous studies of NoCs, primarily derived from traditional data communication network topologies. Some examples of NoC topologies include mesh [7], extended-butterfly fat tree (EFTI) [8], and diametrical mesh (DiaMesh) [9]. Among these, the mesh topology is preferred by NoC designers due to its modularity and scalability. Since the two-dimensional mesh perfectly matches the 2D silicon surface, it is currently the most popular topology used for NoCs in tile-based architectures. Moreover, a 2D mesh topology can be partitioned into smaller meshes, which is a desirable feature for many parallel applications [10]. However, the conventional mesh topology of NoC architecture increases the number of hops when distant nodes communicate with each other, thereby increasing the system size. It requires higher energy consumption, and longer clock cycles to accomplish the communication.To solve this problem inherent in the mesh topology, we propose an extended diagonal mesh (XDMesh) topology that considers the location of nodes situated in remote regions by including diagonal links among these remote regions, which reduces the hop count, latency, energy consumption, and area cost.The rest of this paper is organized as follows. Section 2 discusses related studies of NoC. Section 3 describes the proposed XDMesh topology and its routing algorithm. Section 4 presents the experimental results and analysis. Finally, Section 5 provides conclusions for the paper.

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“…Energy of a network-on-chip. A model of power consumption of network routers was proposed by Ye et al (2002). The bit energy in router (E R bit ) is defined as the dynamic energy consumed while traversing one bit of data through the router:…”

Section: Energy Modelmentioning

confidence: 99%

Energy characteristic of a processor allocator and a network-on-chip

Zydek

Selvaraj

Borowik

et al. 2011

International Journal of Applied Mathematics and Computer Science

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Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

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Analysis of power consumption on switch fabrics in network routers

Cited by 198 publications

References 9 publications

Power efficiency of thin clients

Power efficiency of thin clients

An Extended Diagonal Mesh Topology for Network-on-Chip Architectures

Energy characteristic of a processor allocator and a network-on-chip

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