An Extended Diagonal Mesh Topology for Network-on-Chip Architectures

Abstract

This paper proposes an extended diagonal mesh (XDMesh) topology for network-onchip (NoC) architectures to reduce latency and energy consumption for fast and lowpower communication among remote nodes by including diagonal links in the network. In addition, we compare the performance of the proposed XDMesh with conventional stateof-the art topologies, including mesh, extended-butterfly fat tree (EFTI), and diametrical mesh, in terms of throughput, latency, energy consumption, and area overhead. Experimental results indicate that XDMesh outperforms the conventional topologies in terms of throughput and latency by varying the number of virtual channels and injection rate. Moreover, XDMesh achieves 46.28%, 35.29% and 19.37% lower energy consumption than EFTI, mesh, and diametrical mesh topologies, respectively, and 9.29%, 31.28%, and 15.23% lower silicon area, respectively. 198Copyright ⓒ 2015 SERSC throughput, high bandwidth, reusability, and lower power consumption for communication can be achieved with NoC-based architectures [6].A number of topologies have been proposed in previous studies of NoCs, primarily derived from traditional data communication network topologies. Some examples of NoC topologies include mesh [7], extended-butterfly fat tree (EFTI) [8], and diametrical mesh (DiaMesh) [9]. Among these, the mesh topology is preferred by NoC designers due to its modularity and scalability. Since the two-dimensional mesh perfectly matches the 2D silicon surface, it is currently the most popular topology used for NoCs in tile-based architectures. Moreover, a 2D mesh topology can be partitioned into smaller meshes, which is a desirable feature for many parallel applications [10]. However, the conventional mesh topology of NoC architecture increases the number of hops when distant nodes communicate with each other, thereby increasing the system size. It requires higher energy consumption, and longer clock cycles to accomplish the communication.To solve this problem inherent in the mesh topology, we propose an extended diagonal mesh (XDMesh) topology that considers the location of nodes situated in remote regions by including diagonal links among these remote regions, which reduces the hop count, latency, energy consumption, and area cost.The rest of this paper is organized as follows. Section 2 discusses related studies of NoC. Section 3 describes the proposed XDMesh topology and its routing algorithm. Section 4 presents the experimental results and analysis. Finally, Section 5 provides conclusions for the paper.

Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

“…Md. Hasan Furhad and Jong-Myon Kim [13] proposed an extended diagonal mesh topology (XDMesh) for network-on-chip architecture to reduce average latency and power consumption and increase throughput by including diagonal link in the network. Pengfei Yang and Quan Wang [14] proposed a topology name heterogeneous honeycomb-like network-on-chip topology.…”