Analysis of parasitic effects for pin diode SPDT switch

Abstract

A comparison of insertion loss between a conventional clockwise and a proposed counter-clockwise SiGe pin diode SPDT switch based on an analysis of parasitic effects is presented. In a silicon-based process, the counterclockwise switch is analytically demonstrated to have lower insertion loss than the clockwise switch owing to the alleviation of parasitic effects. Measurement data show good agreement with the presented analysis.

Enhancement technique of insertion loss and linearity for PIN diode switches

“…Furthermore, a SPDT switch (6.25 lm 2 series, 50 lm 2 shunt) shown in Figure 5 is designed and fabricated at 0.18 lm standard SiGe BiCMOS process by using the proposed PIN diode optimization technique. The PIN diode small signal models and SPDT switch designs were performed using the Agilent ADS simulators [8]. The size of PIN diodes in the circuit is selected to achieve the optimized insertion loss and isolation.…”

New approach to fabricate densificated continuous fiber reinforced polytetrafluoroethylene composites with significantly improved interfacial bonding and mechanical properties

“…Furthermore, a SPDT switch (6.25 μm 2 series, 50 μm 2 shunt) shown in Figure 5 is designed and fabricated at 0.18 μm standard SiGe BiCMOS process by using the proposed PIN diode optimization technique. The PIN diode small signal models and SPDT switch designs were performed using the Agilent ADS simulators [8]. The size of PIN diodes in the circuit is selected to achieve the optimized insertion loss and isolation.…”