Analysis of multiple bit upsets (MBU) in CMOS SRAM

Musseau, O.; Gardic, F.; Roche, Ph.; Corbiere, T.; Reed, Robert A.; Buchner, S.; McDonald, P.T.; Melinger, Joseph S.; Tran, Lan; Campbell, A.B.

doi:10.1109/23.556881

Cited by 68 publications

(38 citation statements)

References 27 publications

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“…12 and 13, we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing [11]. In Fig.…”

Section: Discussion On Mcu Increase In the Subthreshold Regionmentioning

confidence: 95%

“…Measurement results show that the MCU rate in the nominal supply voltage region is significantly small and it increases below 0.5 V. To investigate the MCU increase, we measure the dependences of the MCU rate on the body-bias voltage and the distance between well ties. We conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing [11], which is the charge diffusion to multiple nodes induced by a single alpha-particle hit. In addition, reducing the supply voltage possibly enlarges the variation in the soft-error immunity of each memory cell, since circuits become more sensitive to manufacturing variability as the supply voltage is reduced.…”

mentioning

confidence: 99%

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Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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Abstract-This paper presents measurement results of alphaparticle-induced soft errors and multiple-cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 to 0.3 V. We reveal that the soft-error rate (SER) at 0.3 V is six times higher than that at 1.0 V and the MCU rate significantly increases in the subthreshold region. To investigate the reason for the MCU increase, the dependences of the MCU rate on the body-bias voltage and the distance between well ties are examined, and we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing. In addition, the dependence of the variation in the soft-error immunity of each memory cell on the supply voltage is examined, since SRAMs operating in the subthreshold region are sensitive to manufacturing variability. Measurement results indicate that the number of soft errors in each memory cell varies cell by cell, whereas the cause of the variation is explained by the spatial randomness of alpha-particle hits, and a distinct influence of manufacturing variability is not observed even in the subthreshold region.Index Terms-Alpha-particle-induced soft error, multiple-cell upset (MCU), soft-error rate (SER), subthreshold circuit.

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“…12 and 13, we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing [11]. In Fig.…”

Section: Discussion On Mcu Increase In the Subthreshold Regionmentioning

confidence: 95%

mentioning

confidence: 99%

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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“…MBUs are defined as the occurrence of two or more bit upsets, appearing within the same clock cycle from a single particle hit, to distinguish from random multiple hits within a single cycle [Muss96,David09]. While…”

Section: Multi Bit Upsetsmentioning

confidence: 99%

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Gujja

Chellappa

Ramamurthy

et al. 2015

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness

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“…There are different references regarding the reality of error multiplicity on data [16], [17], [25] and [31]. Bit-flips are the consequence of such faults, and depending on the source of the fault, they appear following different patterns.…”

Section: Errors Patternsmentioning

confidence: 99%

“…Besides the possibility of multiple incidences, high energy ions can induce multiple bit upsets if crossing through sensitive adjacent regions -either due to a single ion track or secondary particles caused by an ion collision [16] [17].…”

Section: Physical Faults In Current Semiconductorsmentioning

confidence: 99%