Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Danger, Jean‐Luc; Yashiro, Risa; Graba, Tarik; Mathieu, Yves; Si-Merabet, Abdelmalek; Sakiyama, Kazuo; Miura, Noriyuki; Nagata, Makoto

doi:10.1109/dsd.2018.00090

Cited by 9 publications

(5 citation statements)

References 13 publications

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“…A design with 1024 SR-latches has been implemented in a testchip fabricated in 28nm FD-SOI process and presented in [7]. As a primary goal, it has been built to demonstrate the impact of the body-bias voltage on the properties of a PUF-TRNG architecture.…”

Section: A Architecturementioning

confidence: 99%

“…The NOR gates are built using standard regular threshold voltage V th transistors, but the PMOS transistors of the top NOR and bottom NOR have different and controllable reverse body bias, denoted V B1 and V B2 respectively. It is shown in [7] that the range of V B1, V B2 is quite large to get a high number of SR-latches either stable for PUF, or unstable for latches for TRNG. Another takeaway result is that the optimal pair (V B1, V B2) where there is a maximum of latches stable for PUF happens to be exactly the same as the optimal pair (V B1, V B2) where there is a maximum of latches unstable for TRNG.…”

Section: A Architecturementioning

confidence: 99%

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Special Session: Security Verification & Testing for SR-Latch TRNGs

Bahrami

Ebrahimabadi

Danger

et al. 2023

2023 IEEE 41st VLSI Test Symposium (VTS)

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Secure chips implement cryptographic algorithms and protocols to ensure self-protection (e.g., firmware authenticity) as well as user data protection (e.g., encrypted data storage). In turn, cryptography needs to defer to incorruptible sources of entropy to implement their functions according to their mandatory usage guidance. Typically, keys, nonces, initialization vectors, tweaks, etc. shall not be guessed by attackers. In practice, True Random Number Generators (TRNGs) are in charge of producing such sensitive elements.Fully aware of the central role of TRNGs in the proper implementation of security in chips, stakeholders have been formalizing the requirements recently. The methods to strengthen such requirements are manifold. In this paper, we discuss and apply three of them by targeting the Set-Reset Latch TRNG which is an alternative to Ring-Oscillator (RO) TRNGs as it provides faster throughputs. The first method concerns the confidence in the TRNG being random enough. It explores how the TRNG properties can be reliably predicted by simulation, compared to real silicon experiments. The second aspect dealt with in this paper is the assessment of the TRNG properties over time, i.e., considering the impact of aging in the TRNG properties. Such knowledge is important as secure chips are expected to be in service for a long period, and it would be detrimental to the service they render if the quality of the entropy they deliver would be declining over time. Eventually, the third aspect of this paper is the timely detection of unforeseen failures or malevolent attacks. The mitigation lies in leveraging "health tests" launched prior to using random numbers.This paper focuses on a particular type of TRNG that is not prone to biasing by attackers: it is the so-called Set-Reset Latch (SR-latch) TRNG and exploits a race condition in an arbitration gate. Such kind of TRNG is of great practical interest as an alternative design compared to the mainstream "Ring Oscillator" TRNG, and it is also very amenable to analyses by various sorts of simulations aiming at properly characterizing its security in various operational environments.

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Section: A Architecturementioning

confidence: 99%

Section: A Architecturementioning

confidence: 99%

Special Session: Security Verification & Testing for SR-Latch TRNGs

Bahrami

Ebrahimabadi

Danger

et al. 2023

2023 IEEE 41st VLSI Test Symposium (VTS)

Self Cite

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“…One more recent area of research discusses the potential of various "Physical Unclonable Functions" (PUF). According to various literature of past few years, such PUFs could be able to support mutual authentication protocols [12], or could be used for building a true random number generator (TRNG) [13]. Furthermore, according to very recent literature some approaches even could be reconfigured, a feature which could enable potential regular key updates in future applications as stated in [14].…”

Section: Related Workmentioning

confidence: 99%

Application Study of Hardware-Based Security for Future Industrial IoT

Matischek

Bara

2019

2019 22nd Euromicro Conference on Digital System Design (DSD)

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The stepwise evolution of conventional production facilities into future Smart Factory or Industrial IoT paradigms entails special requirements on future industrial devices and communication networks. Due to the considerably increasing demand of interconnected devices-for internal and even external remote access-various security measures of future industrial equipment must be improved. Therefore, this paper presents an application-and feasibility study of secured communication between today's and future stationary industrial devices-based on the upcoming OPC UA protocol and partially enhanced with hardware-based security.

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“…The authors suggested to include an expensive synchronizer in Clock Domain Signal (CDC) signals to get stable PUF response. A framework of 'body-bias' adjusted voltage on SR-latch timing using FD-SOI technology is presented in [10]. To get correct PUF response, authors employed buffers along the track of top and bottom of latches that suffer from responses biasedness.…”

Section: Background and Related Workmentioning

confidence: 99%

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

Challa

Islam

Katkoori

2019

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

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Physical Unclonable Functions (PUFs) have emerged as a promising solution to identify and authenticate Integrated Circuits (ICs). In this paper, we propose a novel NAND-based Set-Reset (SR) Flip-flop (FF) PUF design for security enclosures of the area-and power-constrained Internet-of-Things (IoT) edge node. Such SR-FF based PUF is constructed during a unique race condition that is (normally) avoided due to inconsistency. We have shown, when both inputs (S and R) are logic high ('1') and followed by logic zero ('0'), the outputs Q and Q can settle down to either 0 or 1 or vice-versa depending on statistical delay variations in cross-coupled paths. We incorporate the process variations during SPICE-level simulations to leverage the capability of SR-FF in generating the unique identifier of an IC. Experimental results for 90nm, 45nm, and 32nm process nodes show the robustness of SR-FF PUF responses in terms of uniqueness, randomness, uniformity, and bit(s) biases. Furthermore, we perform physical synthesis to evaluate the applicability of SR FF PUF on five designs from OpenCores in three design corners. The estimated overhead for power, timing, and area in three design corners are negligible.

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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Cited by 9 publications

References 13 publications

Special Session: Security Verification & Testing for SR-Latch TRNGs

Special Session: Security Verification & Testing for SR-Latch TRNGs

Application Study of Hardware-Based Security for Future Industrial IoT

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

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