Analysis of Low Power 1-bit Adder Cells Using Different XOR-XNOR Gates

Deepa,; Kumar, Vinod

doi:10.1109/cict.2015.21

Cited by 11 publications

(7 citation statements)

References 6 publications

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“…The proposed adder circuits are compared with Deepa, Sampath 6T adder [3] and Reddy, Kavita 6T adder [2]. A comparison table of the measured parameters is given in Table V.…”

Section: Parameter Calculationmentioning

confidence: 99%

“…8. In the previous section, our proposed adders are compared with two different adders and the both adders are designed using only 6 transistors [3,2]. But the truth is that both adders are applicable if the inputs and inverted inputs are available.…”

Section: Parameter Calculationmentioning

confidence: 99%

“…In order to achieve compactness and low power consumption, it is highly in demand to reduce the number of transistors. Pass Transistor Logic (PTL) is employed to reduce the transistor count as well as power dissipation [3]. Although, voltage drop is the main drawback of PTL as logic '1' passing through NMOS transistor is never be equal to the V DD and logic '0' is never be equal to the GND.…”

Section: Introductionmentioning

confidence: 99%

“…Although, voltage drop is the main drawback of PTL as logic '1' passing through NMOS transistor is never be equal to the V DD and logic '0' is never be equal to the GND. But in a processor, there are so many arithmetic units and a large number of adder circuits are needed to be designed in a very limited area [3]. So, the PTL is still in demand for low power IC design.…”

Section: Introductionmentioning

confidence: 99%

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Low Power Full Adder Design Using PTM Transistor Model

Devnath

Biswas

2019

Carpathian Journal of Electronic and Computer Engineering

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At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an efficient full adder, designer should choose an appropriate logic style. In this research, two new model of full-adder circuits are designed and analyzed using Pass Transistor logic in order to reduce power consumption and increase operational speed. The first proposed adder consists of 8 transistors and the second one consists of 10 transistors. LTSPICE is employed for simulating the proposed circuits using16nm low power high-k strained silicon transistor model. The overall performance of the proposed adder circuits and comparative results demonstrate the superiority of the proposed model.

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“…The proposed adder circuits are compared with Deepa, Sampath 6T adder [3] and Reddy, Kavita 6T adder [2]. A comparison table of the measured parameters is given in Table V.…”

Section: Parameter Calculationmentioning

confidence: 99%

Section: Parameter Calculationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low Power Full Adder Design Using PTM Transistor Model

Devnath

Biswas

2019

Carpathian Journal of Electronic and Computer Engineering

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“…The second full adder is the 10T full adder which is having XNOR kind of full adder, this sort of full adder utilizing pass transistor logic (PTL) [9]. This kind of full adder is called static vitality recuperation full adder it having 4T XNOR appeared in figure plan [9]. The disposal of the way in the direction of the position lessens the absolute power utilization through decreasing the small out power utilization.…”

Section: B Xor Full Adder Designmentioning

confidence: 99%

Design and Power Analysis of Vedic Multiplier

Kiruthika*¹,

Sakthi²,

Yuvarani³

2019

IJRTE

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In this article, displays the capacity of decrease the Power, Area in CMOS VLSI blocks. Power in CMOS circuits is mostly consumed for the duration of the transitions of the gates. Thusly, control estimation of CMOS circuits is changed over into progress action estimation. A few methods are utilized to mimic progress exercises of CMOS circuits. The proposed Vedic multiplier is planned by utilizing various strategies of full adder cells. The structure of full adders for low power is gotten and low power blocks are actualized on the arranged multiplier with the outcomes be broke down used for improved execution. The structures are finished by utilizing TANNER S-EDIT tool and recreated utilizing T-SPICE.

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Design of low power, high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical, logical and telecommunication circuit and system application

Bari¹,

Sarkar

2017

Microsyst Technol

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Analysis of Low Power 1-bit Adder Cells Using Different XOR-XNOR Gates

Cited by 11 publications

References 6 publications

Low Power Full Adder Design Using PTM Transistor Model

Low Power Full Adder Design Using PTM Transistor Model

Design and Power Analysis of Vedic Multiplier

Design of low power, high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical, logical and telecommunication circuit and system application

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