Low Power Full Adder Design Using PTM Transistor Model

Abstract

At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an efficient full adder, designer should choose an appropriate logic style. In this research, two new model of full-adder circuits are designed and analyzed using Pass Transistor logic in order to reduce power consumption and increase operational speed. The first proposed adder consists of 8 transistors and the second one consists of 10 transistors. LTSPICE is employed for simulating the proposed circuits using16nm low power high-k strained silicon transistor model. The overall performance of the proposed adder circuits and comparative results demonstrate the superiority of the proposed model.

Design Space Exploration of Low Power Full Adder Across Multiple Logic Styles and Process

“…A 10T full adder in PTL logic style is simulated at 90 nm and 65 nm and the design is evaluated for power consumption and delay against the conventional 28T full adder for minimum PDP and the limitations of CMOS PTL on the designs, signal degradation and floating output node issues are explored [9], [10]. The performance of 8T and 10T full adder in PTL logic using logic level, circuit level and mixed mode implementation is evaluated post layout for power and area with minimum device count [11], [12]. In contrast, full adder circuits with minimum transistor size for low power and optimized device size for minimum PDP are investigated to demonstrate traditional CMOS and mirror topologies for optimal speed-power tradeoff [13].…”