4-bit Wallace and Dadda Multiplier design using novel hybrid 3-2 Counter

Devnath, Bappy Chandra; Biswas, Saroj; Datta, Metali Rani

doi:10.1109/icaict51780.2020.9333511

Cited by 5 publications

(2 citation statements)

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“…The sensor hubs rely on microcontrollers as the preparation capacity is limited. The FPGAs provide optimized phases and target to chip away with economic power and vitality use [5][6][7]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

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This research focuses on critical hardware components of an Internet of Things (IoT) system for reconfigurable processing systems. Single-Instruction Multiple-Data (SIMD) processors have recently been utilized to preprocess data at energy-constrained sensor nodes or IoT gateways, saving significant energy and bandwidth for transmission. Using traditional CPU-based systems to implement machine learning algorithms is inefficient in terms of energy consumption. In the proposed method Single-Instruction Multiple-Data (SIMD) processors are assembled by scaling the largest possible operand value subunits into direct access to the internal memory, where the carry output of each unit is conditionally fed into the next unit based on the implementation of the SIMD Processor design for Internet of Things applications. Each method has evaluated sub-operations that contribute considerably to the overall potential of the design. If the single register file can complete the intended action, a zero (one)-signal is applied to each unit's carry input. Multiplexers combine two or more adders, sending the carry signal from one unit into another if additional units are necessary to compute the sum. The outcome results compare high-speed end device techniques in terms of area and power consumption. The proposed SIMD processor-based IoT healthcare monitoring system with a MIMD processor's performance analysis of comparison clearly demonstrates that the system produces decent outcomes. The suggested system has an area overhead of 85 m 2 , a power usage of 4.10 W, and a time delay of 20 ns.

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Section: Introductionmentioning

confidence: 99%

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

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“…Wallace and Dadda multipliers [18] were created using a brand-new hybrid 3-2 counter by Devnath, et al The suggested method used several AND gates to make partial products, and a good model of an AND gate only needs two transistors. The multipliers were developed using the 65 nm PTM (full form) transistor model.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

2022

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In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

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