Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

Henson, W.K.; Yang, Ni; Kubicek, Stefan; Vogel, Eric M.; Wortman, J. J.; Meyer, K. De; Naem, A.

doi:10.1109/16.848282

Cited by 98 publications

(37 citation statements)

References 30 publications

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“…However, finding and modelling of the several leakage mechanisms are essential for evaluation and minimization of leakage current for low power application [13] [14]. Generally, device non-conducting current ( ) OFF I depends on the supply voltage, threshold voltage, length of the channel, surface/channel doping profile, drain/source junction depth and gate oxide thickness [15]. For long channel devices OFF I mainly originates from the drain-source reverse bias junctions.…”

Section: Introductionmentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

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Section: Introductionmentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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“…The deterioration of the subthreshold slope enhances the off state leakage current and this consequently increases age roll off. It is also observed that the off state current is enhanced as a result of the slashing of the source junction barrier to minority carriers via the drain potential; this effect is known as the DIBL [34]. Retrograde or super steep retrograde profiles are utilised, in order to suppress the SCE [35].…”

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confidence: 99%

Review Paper on New Technology Based Nanoscale Transistor

Talukdar¹,

P.C²,

Agarwal³

2016

MSEJ

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“…1. Two current sources, I GONGS and I GONGD model the direct tunneling leakage when the transistor is on, and two current source, I EDTSG and I EDTSD model the Edge-Directed-Tunneling (EDT) when the transistor is off [15]. The macro-model is similar to the one found in [9], except that it also includes the EDT current.…”

Section: Model For I Gatementioning

confidence: 99%

“…At the 70nm technology node, CMOS processes will have oxide thicknesses of 1.2nm to 1.6nm [1]. Since the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) gate tunneling leakage current increases exponentially with a reduced oxide thickness [15], gate tunneling leakage power dissipation will grow to be a significant fraction of overall chip power dissipation in modern, deep-submicron (< 0.10µm) processes [12] [18]. As the gate oxide thickness gets thinner, gate tunneling leakage could surpass weak inversion and drain-induced-barrier-lowering leakage as the dominant leakage mechanism in future technologies [8] [13] [10].…”

Section: Introductionmentioning

confidence: 99%