Analysis of high-speed PCB with SiC devices by investigating turn-off overvoltage and interconnection inductance influence

Noppakunkajorn, Jukkrit; Han, Di; Sarlioglu, Bulent

doi:10.1109/apec.2014.6803675

Cited by 13 publications

(8 citation statements)

References 17 publications

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“…Considering that large Lds also causes large turn-on and turn-off overvoltage as in [8], [21], [24], [25], thus Lds should be controlled as small as possible by optimal PCB layout and routing of power loop at the very beginning of power converter design.…”

Section: Optimal Design Of Power Loop Stray Inductancementioning

confidence: 99%

Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Xiao

Zhao

et al. 2021

IEEE Access

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Gallium nitride high electron mobility transistor (GaN HEMT) is liable to gate false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the widely adopted phase-leg topology due to its low threshold voltage and high switching speed. Without considering the gate loop stray inductance, gate internal resistance, nonlinearity of parasitic capacitances and power loop stray parameters, traditional false turn-on analytical method is insufficient to support accurate analysis. And it has been found that GaN HEMT gate-source parasitic capacitance Cgs previously assumed constant is otherwise highly nonlinear and has strong impacts on the gate crosstalk voltage. This paper has measured Cgs by vector network analyzer and constructed an accurate nonlinear model of Cgs, based on which an accurate GaN HEMT behavior model is further fulfilled. The accuracy of the proposed behavior model has been verified by large amounts of experiment results. The proposed GaN HEMT model is used to accurately calculate gate crosstalk voltage and switching losses. Besides, false turn-on induced extra loss has been calculated and is adopted as a criterion to evaluate the severity of false turn-on and optimal design method for false turn-on suppression has been detailed further.

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Section: Optimal Design Of Power Loop Stray Inductancementioning

confidence: 99%

Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Xiao

Zhao

et al. 2021

IEEE Access

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“…The next step is to derive the expression for vDSL as a function of initial drain current Io using the equivalent circuit, which gives the rule for snubber components design. Applying KCL and KVL to the equivalent circuit gives the dynamics in (17). The snubber design starts with deriving an equivalent circuit of Figure 7a using the high-frequency minimization [27].…”

Section: Rc Snubber For Suppression Of Parasitic Ringingmentioning

confidence: 99%

Section: ( ) ( )mentioning

confidence: 99%

Suppression of Switching Crosstalk and Voltage Oscillations in a SiC MOSFET Based Half-Bridge Converter

Zaman

Zheng

et al. 2018

Energies

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The silicon carbide (SiC) MOSFET is characterized by high operating voltage, temperature, switching frequency and efficiency which enables a converter to achieve high power density. However, at high switching frequency, the crosstalk phenomenon occurs when the gate voltage spike introduced by high dv/dt and voltage ringing forces false turn-on of SiC MOSFET which causes a crow-bar current thereby increasing switching losses. In order to increase the immunity against the crosstalk phenomenon in a half-bridge configuration, this paper presents a gate driver for SiC MOSFET capable of generating the negative turn-off voltage without using a negative power supply. In addition, the effect of parasitic inductances on the switching response is analyzed and an RC snubber is designed using high-frequency based circuit reduction technique to dampen the switching ringing. The performance of the proposed gate driver and the designed RC snubber is validated using simulation and experiment at the 1 MHz switching frequency. The results show that the proposed gate driver with RC snubber eliminates crosstalk by maintaining any spurious gate spike below the gate threshold voltage.

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“…However, those associated with printed circuit board (PCB) wires or with decoupling capacitors are not modeled accurately. Noise waveforms of this type of converters are known sensitive to small parasitic elements, and the accurate modeling of parasitic elements as in [21,22] is one of our future works.…”

Section: Transient Characteristicmentioning

confidence: 99%

Modeling of interelectrode parasitic elements of V-groove SiC MOSFET

Zhou

Shintani

Hiromoto

et al. 2018

NOLTA

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We propose a physics-based model of interelectrode parasitic elements of a Vgroove SiC power MOSFET with buried players. The proposed model considers the voltage dependence of parasitic resistances and capacitances on the basis of the observations through technology computer aided design (TCAD) simulations. The gate-voltage dependence of the body diode is also modeled in accordance with device physics. Through comparison with measurement results, it is demonstrated that the proposed model successfully reproduces both I-V and C-V characteristics. The transient behavior using a buck converter is also well reproduced.

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Analysis of high-speed PCB with SiC devices by investigating turn-off overvoltage and interconnection inductance influence

Cited by 13 publications

References 17 publications

Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Suppression of Switching Crosstalk and Voltage Oscillations in a SiC MOSFET Based Half-Bridge Converter

Modeling of interelectrode parasitic elements of V-groove SiC MOSFET

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