Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Abstract

Gallium nitride high electron mobility transistor (GaN HEMT) is liable to gate false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the widely adopted phase-leg topology due to its low threshold voltage and high switching speed. Without considering the gate loop stray inductance, gate internal resistance, nonlinearity of parasitic capacitances and power loop stray parameters, traditional false turn-on analytical method is insufficient to support accurate analysis. And it has been found that GaN HEMT gate-source parasitic capacitance Cgs previously assumed constant is otherwise highly nonlinear and has strong impacts on the gate crosstalk voltage. This paper has measured Cgs by vector network analyzer and constructed an accurate nonlinear model of Cgs, based on which an accurate GaN HEMT behavior model is further fulfilled. The accuracy of the proposed behavior model has been verified by large amounts of experiment results. The proposed GaN HEMT model is used to accurately calculate gate crosstalk voltage and switching losses. Besides, false turn-on induced extra loss has been calculated and is adopted as a criterion to evaluate the severity of false turn-on and optimal design method for false turn-on suppression has been detailed further.

A Comprehensive Review of GaN-Based Bi-directional On-Board Charger Topologies and Modulation Methods

“…Moreover, practically, this method is recommended for soft switching or multi-level [85] applications where the switching dV/dt rate is limited. On the other hand, a negative turn-off voltage is preferred, as shown in Figure 6b, to increase the noise immunity against capacitive coupling via C gd due to high dV/dt rates [86] and ringing at the driver stage [18], especially hard switching and high-power applications, e.g., CCM bridge-less PFC for stage of an OBC, which, however, increases the conduction loss during dead time in reverse conduction mode where the voltage drop across source and drain is much higher than the forward voltage of a MOSFET body diode [9]. Since minimal dead time is not necessarily optimal over the entire operating range due to soft switching ZVS requirements [57], conduction loss during dead time can be significant for both light loads and heavy loads [87].…”

A gate driver for parallel connected MOSFETs with crosstalk suppression

“…Although the mechanism generating the pulse exists in all types of MOSFETs regardless of their material, SiC devices suffer the most. If unaddressed, the generated voltage can easily reach the threshold level and cause a shoot-through or thermal runaway [7] . To increase the margin between the threshold level and gate voltage in a turn-off state, the negative shift of the minimal gate voltage became a rule of thumb if SiC devices were used in the design.…”