Analysis of floating-body-induced leakage current in 0.15 /spl mu/m SOI DRAM

Terauchi, Mamoru; Yoshimi, M.

doi:10.1109/soi.1996.552532

Cited by 6 publications

(5 citation statements)

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“…The lowering of the potential decreases the forward current of the p-n junction and slows the ejection of the remaining holes. It is known that the potential in the body (channel) region decreases logarithmically because of the above effect [28]. This effect also occurs in conventional partially depleted SOI-MOSFETs, and it induces the history effect and pass-gate leakage [29].…”

Section: Resultsmentioning

confidence: 99%

Transient Characteristics on Super-Steep Subthreshold Slope “PN-Body Tied SOI-FET” — Simulation and Pulse Measurement —

Mori

Ida

Endo

2020

IEICE Trans. Electron.

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In this study, the transient characteristics on the supersteep subthreshold slope (SS) of a PN-body tied (PNBT) silicon-oninsulator field-effect transistor (SOI-FET) were investigated using technology computer-aided design and pulse measurements. Carrier charging effects were observed on the super-steep SS PNBT SOI-FET. It was found that the turn-on delay time decreased to nearly zero when the gate overdrive-voltage was set to 0.1-0.15 V. Additionally, optimizing the gate width improved the turn-on delay. This has positive implications for the low speed problems of this device. However, long-term leakage current flows on turn-off. The carrier lifetime affects the leakage current, and the device parameters must be optimized to realize both a high on/off ratio and high-speed operation.

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Section: Resultsmentioning

confidence: 99%

Transient Characteristics on Super-Steep Subthreshold Slope “PN-Body Tied SOI-FET” — Simulation and Pulse Measurement —

Mori

Ida

Endo

2020

IEICE Trans. Electron.

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“…This channel width can be reduced by lowering V th and/or the channel length reduction. Since DTMOS devices have an ideal subthreshold swing of 60 mV/dec at room temperature, 9,10) a 60 mV reduction in V th corresponds to a tenfold increase in channel width. )…”

Section: At Is Calculated Asmentioning

confidence: 99%

“…1, both band bending, S 0 , and gate depletion layer width, w 0 , in a DTMOS are always fixed due to the gate-to-body connection. 9,10) Therefore the surface potential change (Á S ) in a DTMOS is exactly the same as the gate voltage change (ÁV g ), i.e., Á S ÁV g . 5,9,10) Note that an alternative equation, 11) ( S : surface potential, B ¼ ðk B T=qÞ lnðN A =n i Þ, k B : Boltzmann constant, T: absolute temperature, q: elementary charge, N A : substrate impurity concentration, n i : intrinsic impurity concentration) both the DTMOS and the conventional MOSFET are considered to be in the subthreshold region where drain current varies exponentially with S .…”

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confidence: 99%

“…9,10) Therefore the surface potential change (Á S ) in a DTMOS is exactly the same as the gate voltage change (ÁV g ), i.e., Á S ÁV g . 5,9,10) Note that an alternative equation, 11) ( S : surface potential, B ¼ ðk B T=qÞ lnðN A =n i Þ, k B : Boltzmann constant, T: absolute temperature, q: elementary charge, N A : substrate impurity concentration, n i : intrinsic impurity concentration) both the DTMOS and the conventional MOSFET are considered to be in the subthreshold region where drain current varies exponentially with S . Therefore the subthreshold swing, S, of the DTMOS is represented exactly as S DTMOS ¼ ðk B T=qÞ ln 10 whereas that of conventional bulk MOSFET is written as…”

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confidence: 99%

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Temperature Dependence of the Subthreshold Characteristics of Dynamic Threshold Metal–Oxide–Semiconductor Field-Effect Transistors and Its Application to an Absolute-Temperature Sensing Scheme for Low-Voltage Operation

Terauchi

2007

jjap

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Communicated by B. F. J. Schonland ; MS. received 5thJuly 1956 and in revised form 26th February 1957 satlonal Telecommunications Research Laboratory of the South African Council for,@styact. Radar observations, on a wavelength of 50 cm, of inter-stroke lightning processes provide the following information on the nature of the charged column and the manner in which it is discharged: (a) Inter-stroke junction streamer activity is most intense and most prolonged in the lower regions, that is, at heights ranging from 4-7 km. (b) Vertical development of the junction streamers may on occasion take place steadily to a height of about 10 kilometres. The velocities are in good agreement with those derived by Malan and Schonland. The junction streamer activity is somewhat less Intense in the upper regions and tends to disappear while activity still persists In the lower regions. (c) The lower height limit of junction streamer activity remains at a more or less constant height throughout the flash. ( d ) The horizontal extent of the junction streamer activity in the lower regions is frequently of the order of 14-2 kilometres. (e) The echoing properties of the junction streamers actually decrease during the latter part of the inter-stroke period and a further stroke does not occur until this decrease has taken place. (f) A stroke may take place from one or more regions in the charged column, without affecting appreciably the junction streamer process in another region which will nevertheless contribute to a later stroke in the same lightning discharge.Modifications to the tentative description of the inter-stroke processes given by Malan and Schonland are suggested which would explain these results.Some information has been gained on the nature and intensity of the noise radiated by lightning at 600 Mc/s. I n particular it appears that at this frequency the noise is radiated from comparatively localized sources and may possibly be associated with the stepped and dart leader processes.

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“…The floating-body-induced degradation in dynamic retention time can be alleviated by raising the threshold voltage to reduce the subthreshold leakage (at the expense of cell performance) [34]. One can also try to create a leaky bodysource junction (to lower the current gain of the parasitic bipolar transistor) and reduce the drain-body coupling to lower the floating-body voltage [34]. This requires detailed device design and process window tradeoff, especially for the case of leaky body-source junction, where the junction leakage must remain substantially lower than the subthreshold leakage of the MOSFET.…”

Section: Dynamic Random Access Memoriesmentioning

confidence: 99%

SOI for digital CMOS VLSI: design considerations and advances

Chuang

Anderson

1998

Proc. IEEE

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This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAM's), dynamic random access memories (DRAM's), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

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Analysis of floating-body-induced leakage current in 0.15 /spl mu/m SOI DRAM

Cited by 6 publications

References 0 publications

Transient Characteristics on Super-Steep Subthreshold Slope “PN-Body Tied SOI-FET” — Simulation and Pulse Measurement —

Transient Characteristics on Super-Steep Subthreshold Slope “PN-Body Tied SOI-FET” — Simulation and Pulse Measurement —

Temperature Dependence of the Subthreshold Characteristics of Dynamic Threshold Metal–Oxide–Semiconductor Field-Effect Transistors and Its Application to an Absolute-Temperature Sensing Scheme for Low-Voltage Operation

SOI for digital CMOS VLSI: design considerations and advances

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