Analysis of evolutionary techniques for the automated implementation of digital circuits

Zarifi, Mohammad H.; Satvati, Hajar; Baradarannia, Mahdi

doi:10.1016/j.eswa.2015.06.005

Cited by 7 publications

(2 citation statements)

References 14 publications

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“…Genetic algorithms (GAs) belong to a large family of stochastic search methods that mimic the process of natural biological evolution called EAs 1 . GA is a common and powerful search technique widely used in computing, to find exact or approximate solutions and to solve optimization and search‐related problems 12,13 . In EHW, GA is used to find a feasible circuit (solution) that satisfies some specification or truth table.…”

Section: Introductionmentioning

confidence: 99%

On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

Shang

Chen

Peng

2019

Concurrency and Computation

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This paper presents the on-chip evolution system of combinational logic circuits by a new hybrid algorithm known as improved genetic-simulated annealing algorithm (IGASA). IGASA is based on the concept and principles of genetic algorithm (GA) and simulated annealing (SA). The main idea is to combine GA's global search ability with the advantage of SA's fast convergence to reach an optimal solution. In this paper, a new mutation operation and a repeated annealing (RA) process are introduced to overcome the premature convergence of the standard GA and the large number of searches in the later period. An elitist strategy to enhance convergence characteristic of the proposed algorithm is incorporated to better speed up the evolution process. In addition, the new algorithm is implemented in a new evolvable platform using Intel Cyclone V FPGA with an embedded ARM microprocessor. Comparison of the performance of the improved algorithm to the pure GASA algorithm and standard GA is presented on a number of case studies. The experiment results demonstrate that feasible circuits are always achieved by the IGASA algorithm unlike with other algorithms and the number of generations required is less. KEYWORDS ARM processor, combinational logic circuits, evolvable hardware (EHW), field programmable system-on-chip (FPSoC), improved genetic-simulated annealing (IGASA) 1 INTRODUCTION Evolvable hardware (EHW) is a thriving area of research which uses the genetic algorithm (GA) to construct novel circuits without manual engineering. 1 It is also a new field at the confluence of reconfigurable devices, autonomous systems, artificial intelligence, and automatic design. 2 A complete hardware evolution system usually consists of two main elements: evolutionary algorithm (EA) 3 and reconfigurable hardware device. Specifically, EHW is generally classified into two major classes: extrinsic EHW 4 and intrinsic EHW. 5 The biggest difference between extrinsic EHW and intrinsic EHW is whether the chromosome is evaluated by software simulation or in hardware. In recent years, the emergence of Field Programmable System-on-Chips (FPSoCs) 6 has brought hardware evolution to a third dimension, called On-chip evolution. 7 The FPSoC implements the entire EHW system from a single chip by providing embedded processors (such as ARM cores). By constructing a virtual reconfigurable circuit (VRC) 8 layer, the problem of reconfiguration limitations of commercial FPGA can be well overcome. FPSoCs allow power consumption and board size to be reduced, and reliability and performance (thanks to on-chip communications) to be increased compared to external multichip solutions. 9 However, despite the potential advantages of the FPGA-ARM single-chip platform, the need for designers to have good knowledge and expertise in both hardware and software domains makes this area of research reported in very few works, 10 and all of those works only targeting Xilinx Zynq-7000 devices. 11 Therefore, in order to analyze the detailed performance of different FPSoCs that evolve ...

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Section: Introductionmentioning

confidence: 99%

On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

Shang

Chen

Peng

2019

Concurrency and Computation

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“…Data-driven modeling has become a powerful technique in different areas of engineering, such as industrial data analysis (Luo et al, 2015;Li et al, 2017), circuits analysis and design (Ceperic et al, 2014;Shokouhifar & Jalali, 2015;Zarifi et al, 2015), signal processing (Yang et al, 2005;Volaric et al, 2017), empirical modeling (Gusel & Brezocnik, 2011;Mehr & Nourani, 2017), system identification (Guo & Li, 2012;Wong et al, 2008), etc. For a concerned data-driven modeling problem with n input variables, we aim to find a performance function f * : R n → R that best explains the relationship between input variables x = x 1 x 2 • • • x n T ∈ R n and the target system (or constrained system) based on a given set of sample points S = x (1) x (2) • • • x (N ) T ∈ R N ×n .…”

Section: Introductionmentioning

confidence: 99%

A multilevel block building algorithm for fast modeling generalized separable systems

Chen

Luo

Jiang

2018

Expert Systems with Applications

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Data-driven modeling plays an increasingly important role in different areas of engineering. For most of existing methods, such as genetic programming (GP), the convergence speed might be too slow for large scale problems with a large number of variables. It has become the bottleneck of GP for practical applications. Fortunately, in many applications, the target models are separable in some sense. In this paper, we analyze different types of separability of some real-world engineering equations and establish a mathematical model of generalized separable system (GS system). In order to get the structure of the GS system, a multilevel block building (MBB) algorithm is proposed, in which the target model is decomposed into a number of blocks, further into minimal blocks and factors. Compare to the conventional GP, MBB can make large reductions to the search space. This makes MBB capable of modeling a complex system. The minimal blocks and factors are optimized and assembled with a global optimization search engine, low dimensional simplex evolution (LDSE). An extensive study between the proposed MBB and a state-of-the-art data-driven fitting tool, Eureqa, has been presented with several man-made problems, as well as some real-world problems. Test results indicate that the proposed method is more effective and efficient under all the investigated cases.

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An evolvable hardware method based on elite Partheno-Genetic Algorithm

Liu

Wang

2021

Applied Soft Computing

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Analysis of evolutionary techniques for the automated implementation of digital circuits

Cited by 7 publications

References 14 publications

On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

A multilevel block building algorithm for fast modeling generalized separable systems

An evolvable hardware method based on elite Partheno-Genetic Algorithm

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