On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

Abstract

This paper presents the on-chip evolution system of combinational logic circuits by a new hybrid algorithm known as improved genetic-simulated annealing algorithm (IGASA). IGASA is based on the concept and principles of genetic algorithm (GA) and simulated annealing (SA). The main idea is to combine GA's global search ability with the advantage of SA's fast convergence to reach an optimal solution. In this paper, a new mutation operation and a repeated annealing (RA) process are introduced to overcome the premature convergence of the standard GA and the large number of searches in the later period. An elitist strategy to enhance convergence characteristic of the proposed algorithm is incorporated to better speed up the evolution process. In addition, the new algorithm is implemented in a new evolvable platform using Intel Cyclone V FPGA with an embedded ARM microprocessor. Comparison of the performance of the improved algorithm to the pure GASA algorithm and standard GA is presented on a number of case studies. The experiment results demonstrate that feasible circuits are always achieved by the IGASA algorithm unlike with other algorithms and the number of generations required is less. KEYWORDS ARM processor, combinational logic circuits, evolvable hardware (EHW), field programmable system-on-chip (FPSoC), improved genetic-simulated annealing (IGASA) 1 INTRODUCTION Evolvable hardware (EHW) is a thriving area of research which uses the genetic algorithm (GA) to construct novel circuits without manual engineering. 1 It is also a new field at the confluence of reconfigurable devices, autonomous systems, artificial intelligence, and automatic design. 2 A complete hardware evolution system usually consists of two main elements: evolutionary algorithm (EA) 3 and reconfigurable hardware device. Specifically, EHW is generally classified into two major classes: extrinsic EHW 4 and intrinsic EHW. 5 The biggest difference between extrinsic EHW and intrinsic EHW is whether the chromosome is evaluated by software simulation or in hardware. In recent years, the emergence of Field Programmable System-on-Chips (FPSoCs) 6 has brought hardware evolution to a third dimension, called On-chip evolution. 7 The FPSoC implements the entire EHW system from a single chip by providing embedded processors (such as ARM cores). By constructing a virtual reconfigurable circuit (VRC) 8 layer, the problem of reconfiguration limitations of commercial FPGA can be well overcome. FPSoCs allow power consumption and board size to be reduced, and reliability and performance (thanks to on-chip communications) to be increased compared to external multichip solutions. 9 However, despite the potential advantages of the FPGA-ARM single-chip platform, the need for designers to have good knowledge and expertise in both hardware and software domains makes this area of research reported in very few works, 10 and all of those works only targeting Xilinx Zynq-7000 devices. 11 Therefore, in order to analyze the detailed performance of different FPSoCs that evolve ...

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