Analysis of Drain Field and Hot Carrier Stability of Poly-Si Thin Film Transistors

Abstract

Hot carrier instabilities in poly-Si thin film transistors (TFTs) are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n+ doping profile in the drain and the two-dimensional (2D) coupling of the x and y components of the electric field between the gate and drain. The density of trapping states in the poly-Si film, however, has a much less significant impact on the field. Further, it is shown that improving the properties of the poly-Si film tends to have an adverse affect on hot carrier stability. Consequently, it is concluded that drain field relief is essential for hot carrier stability of n-channel poly-Si TFTs. It is shown that gate overlapped lightly doped drain (GOLDD) architectures can be used to relieve the drain field without introducing series resistance. Stable TFTs have been fabricated with GOLDD, consistent with circuit operation up to drain biases of 20 V. GOLDD is also effective in reducing the field enhanced leakage current in the off-state.

Source-gated transistors in poly-silicon

“…The characteristics have the main features of a SGT, namely a low saturation voltage and high output impedance. The characteristics of bottom-gated FET structures with ohmic source regions showed much lower output impedances and the saturation voltage changed by approximately 1 V for every additional volt on the gate and were similar to these found in top-gated structures [11]. Furthermore the saturation current of the SGT at a given gate voltage was independent of d, the length of the channel of the parasitic FET (Fig.…”

“…However it is in this region of the FET that the current is most sensitive to small changes in threshold voltage. In contrast, the SGT can be operated at high gate voltages well away from the threshold where the effects of threshold variations and instability are negligible, particularly since device stability is sensitive to drain field rather than gate field [11].…”

Intrinsic Gain in Self-Aligned Polysilicon Source-Gated Transistors

“…In this paper we are concerned with analog circuits, and in particular the amplification factor or intrinsic gain of the thin-film transistor. It is difficult to obtain high intrinsic gain in conventional polysilicon FETs because the output characteristic is degraded by the so-called "kink effect" in which minority carriers generated in the high field region at the drain under saturation drift back toward the source and increase the drain current via the bipolar effect [3][4][5]. Therefore, output impedance is only large for small drain voltages.…”

Thermal analysis of amorphous oxide thin-film transistor degraded by combination of joule heating and hot carrier effect

“…However, the degradation phenomenon induced by the Joule heating of oxide TFT 6 has not been investigated compared with that of Si TFTs. [7][8][9][10] Fujii et al have reported the self-heating effect of IGZO TFTs induced by Joule heating under voltage operation. 11 However, the result indicated in their paper has not been sufficient for explaining the degradation phenomenon of the oxide TFTs under electrical stress.…”