Thermal analysis of amorphous oxide thin-film transistor degraded by combination of joule heating and hot carrier effect

Abstract

Demonstration and characterization of an ambipolar high mobility transistor in an undoped GaAs/AlGaAs quantum well Appl. Phys. Lett. 102, 082105 (2013) Investigation of the charge transport mechanism and subgap density of states in p-type Cu2O thin-film transistors Appl. Phys. Lett. 102, 082103 (2013) Negative gate-bias temperature stability of N-doped InGaZnO active-layer thin-film transistors Appl. Phys. Lett. 102, 083505 (2013) A pH sensor with a double-gate silicon nanowire field-effect transistor Appl. Phys. Lett. 102, 083701 (2013) Extrinsic and intrinsic photoresponse in monodisperse carbon nanotube thin film transistors Appl. Phys. Lett. 102, 083104 (2013) Additional information on Appl. Phys. Lett.

Thermal distribution in amorphous InSnZnO thin‐film transistor

“…Recently, we have reported the thermal distribution of ITZO TFT under various bias voltages and the voltage dependence of degradation phenomena [14]. Consequently, we concluded that the degradation phenomena were caused by combination of Joule heating and impact ionization [15][16][17][18].…”

Analysis of Instability Mechanism under Simultaneous Positive Gate and Drain Bias Stress in Self-Aligned Top-Gate Amorphous Indium-Zinc-Oxide Thin-Film Transistors

“…This degradation effects were electron-hole pairs and self-heating [5]. However, in terms of investigating the degradation mechanism, there have been controversial thoughts: hole trapping into back channel by electron-hole pairs [5,6], donor-state creation at channel layer [7,8]. Such mechanisms have not been quantitatively clarified yet including which mechanism is responsible for the DV T .…”

“…Also, such instability issues have been analyzed by many research groups and some of them have focused on the negative shift of threshold voltage (DV T ) under SPGDBS as well. This degradation effects were electron-hole pairs and self-heating [5]. However, in terms of investigating the degradation mechanism, there have been controversial thoughts: hole trapping into back channel by electron-hole pairs [5,6], donor-state creation at channel layer [7,8].…”

Comparative Analysis on Positive Bias Stress-Induced Instability under High VGS/Low VDSand Low VGS/High VDSin Amorphous InGaZnO Thin-Film Transistors

“…The positive bias stress (PBS)-induced instability is of special importance in terms of the active matrix organic light emitting diode (AMOLED) displays because applying both the positive gate-to-source voltage (V GS ) and positive drain-to-source voltage (V DS ) corresponds with the driving condition of AMOLED [3][4][5]. Although various V GS /V DS conditions including the high V DS need to be investigated for optimizing the driving scheme of the AMOLED backplane driven by a-IGZO TFTs, most of the previous works have been focused on the cases of V GS higher than or equal to V DS [6][7][8].…”