Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections

Nsengiyumva, Patrick; Massengill, L.W.; Alles, Michael L.; Bhuva, B. L.; Ball, D. R.; Kauppila, J. S.; Haeffner, T. D.; Holman, W.T.; Reed, Robert A.

doi:10.1109/tns.2016.2620940

Cited by 47 publications

(16 citation statements)

References 17 publications

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“…In our case, we preferred to use a Gaussian ion track structure because it is more frequently used in device simulation studies, and because it provides a more realistic ion track structure, as experimentally validated in [29]. Previous studies [4] conclude that for FinFET technology the characteristic ion-track radius of the Gaussian function should have a value close to 10 nm for the best accuracy of the results.…”

Section: A Ion Trackmentioning

confidence: 99%

“…The change in device structure from planar to FinFET impacts the sensitive area and the charge collection process after an ion strike [4]. In conventional CMOS devices all the area under the device collects the charge produced by the ion, but in the bulk FinFET only the area under the fin collects the charge generated by the ion impact ( Fig.…”

Section: Introductionmentioning

confidence: 99%

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Active Radiation-Hardening Strategy in Bulk FinFETs

et al. 2020

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Section: A Ion Trackmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Active Radiation-Hardening Strategy in Bulk FinFETs

et al. 2020

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“…The heavy-ion injection in TCAD simulation follows the methodology presented in [12], considering a Gaussian charge distribution with a track radius of 10nm. To model the worstcase scenario of such particle strike, the charge track length should be longer than the fin height, with normal incidence over the drain of the sensitive transistor (off-state transistor).…”

Section: B Modeling Ion Strikementioning

confidence: 99%

“…In [12], a comparison of SEE effects between a 16 nm bulk FinFET and a 28 nm bulk planar technology was carried out. This study shows that low-LET particles may cause transients in FinFETs when hitting the fin region.…”

Section: Introductionmentioning

confidence: 99%

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Copetti

Medeiros

Taouil

et al. 2020

2020 IEEE Latin-American Test Symposium (LATS)

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Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET-based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFETbased SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

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“…Anyway, FPGA utilization in safety or mission critical applications is still limited due to the dependability issues related to radiation sensitivity. In fact, even if recent studies indicate that the new FinFET technology has a lower Single-Event Effect sensitivity than previous generation bulk processes [1]- [3], the technology scaling on the other side, increases the device density and consequently the probability that incident particles hit more nodes [4]. In fact, the continuous size shrinking of FPGA's transistors on one hand improves the device density, power consumption and performances and on the other hand, increases the sensitivity regarding radiation-induced errors such as Single-Event Upsets (SEUs) and Single-Event Transients (SETs).…”

Section: Introductionmentioning

confidence: 99%

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Sterpone

Azimi

Bozzoli

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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SRAM-based FPGA devices manufactured in FinFET technologies provide performances and characteristics suitable for avionics and aerospace applications. The estimation of error rate sensitivity to harsh environments is a major concern for enabling their usage on such application fields. In this paper, we propose a new estimation approach able to consider the radiation effects on the configuration memory and logic layer of FPGAs, providing a comprehensive Application Error Rate probability estimation. Experimental results provide a comparison between radiation test campaigns, which demonstrates the feasibility of the proposed solution.

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Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections

Cited by 47 publications

References 17 publications

Active Radiation-Hardening Strategy in Bulk FinFETs

Active Radiation-Hardening Strategy in Bulk FinFETs

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

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