Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer

Kondekar, P. N.; Parikh, Chetan D.; Patil, Mukesh D.

doi:10.1109/psec.2002.1023067

Cited by 19 publications

(11 citation statements)

References 4 publications

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“…5(c) shows ON/OFF state output characteristics, where V DS increases up-to the BV, for different value of V GS . The maximum BV obtained by simulation is 590V in OFF state and analytically obtain BV is 650V from [15]. In this paper reported value of the R DSon A is lowest than that of the SJ VDMOS fabricated by conventional method.…”

Section: Resultsmentioning

confidence: 56%

“…Substrate used for fabrication is silicon faced n-type wafer with phosphorus as dopant of concentration 3 × 10 18 /cm 3 . An epitaxial drift layer is grown with phosphorus doping 6 × 10 15 /cm 3 using chemical vapor phase deposition (CVD), and then trench p-pillar is formed using DRI at 1100 • C with doping conNet Doping/cm 3 1.5x10 19 2.3x10 18 2.5x10 17 3.1x10 16 3.1x10 15 5.1x10 centration of boron 6 × 10 15 /cm 3 . After forming n-p pillar, selectively boron ions are implanted based on Texas model implementation [12] to form the p+ region above the p-pillar with 80KeV and diffused at 1100 • C. Then n + region are formed within the p + region by implanting arsenic ions with 100KeV and diffused at 1100 • C. Activation of the implanted ions are done through rapid thermal annealing at 1150 • C for 5 minutes.…”

Section: Device Design Process Flow Stepmentioning

confidence: 99%

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Optimized process design flow for fabrication of superjunction VDMOS for enhanced R<inf>DSon</inf>A

Naugarhiya

Kondekar

2014

2014 11th International Symposium on Electronics and Telecommunications (ISETC)

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In this paper, we proposed a simple and optimized process design flow for the fabrication of Silicon Charge Balance (CB) Super Junction (SJ) Vertical Double Diffused MOS (VD-MOS). Deep Reactive Ion etching (DRI) is used for forming trench p-pillar with process simulation, which reduces the design complexity and number of steps required for device fabrication. The trench p-pillar that has been formed at 1100 • C using DRI causes crystal defects. We remove these defects by annealing at 1150 • C which results in reduction of Area Specific ON Resistance across Source/Drain (S/D) (RDSonA). The proposed process device has Breakdown Voltage (BV) 590V , RDSonA 3.1mΩcm 2 and maximum operating switching frequency (fT )1.027GHz.

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Section: Resultsmentioning

confidence: 56%

Section: Device Design Process Flow Stepmentioning

confidence: 99%

Optimized process design flow for fabrication of superjunction VDMOS for enhanced R<inf>DSon</inf>A

Naugarhiya

Kondekar

2014

2014 11th International Symposium on Electronics and Telecommunications (ISETC)

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“…As the co-existence of PM and CB effect, the BV of HKTMOS is higher than that of the SJ and shows strong tolerance towards the varying of the drift region doping. Whereas the BV of the SJ is sensitive to the drift region doping [20]. Consequently, the drift region doping of SJ must be low to achieve similar BV with HKTMOS and therefore an objectively FOM(H) comparison.…”

Section: Simulation Verification and Discussionmentioning

confidence: 99%

Investigation of a Novel High-Permittivity Trench MOS Device with Small Figures of Merit

Li¹,

Xiao²

2018

IJCTE

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We propose a vertical high-permittivity trench power metal oxide semiconductor (HKTMOS) device with an alternating N&P drift regions and high-permittivity (HK) trench sandwiched in between. The unique structure guarantees uniform potential distribution for a wide voltage range at the blocking state owing to both the HK potential modulation effect and the superjunction (SJ) charge balance. The specific on-resistance (R ons ) of HKTMOS is orders of magnitude lower than the SJ counterparts in the on-state because of the strong accumulation effect brought by the HK trenches. Although the gate charges also significantly rise because of the accumulation, the figures of merit (FOM) of HKTMOS still decrease considerably compared to the SJ under the same device length condition. An expression for the FOM is derived, demonstrating that the FOM of HKTMOS is proportional to the square of the HK trench depth, which agrees with the simulation results well. The simulation indicates that within the BV range of 500~2000 V, the R ons of HKTMOS is 1~2 orders of magnitude lower than that of SJ, and its FOM is 17.4%~44.1% that of SJ under the same device size condition. Furthermore, HKTMOS also demonstrates better charge imbalance tolerance than SJ.Index Terms-High permittivity, figures of merit, specific on resistance, power MOS.

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“…and of the total MOSFET losses. Hence, (12) and (15) have to be solved iteratively by the application of (10) and (16).…”

Section: Power Mosfet Lossesmentioning

confidence: 99%

On the Tradeoff Between Input Current Quality and Efficiency of High Switching Frequency PWM Rectifiers

Hartmann

Ertl

Kolar

2012

IEEE Trans. Power Electron.

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Due to their basic physical properties, power MOSFETs exhibit an output capacitance C oss that is dependent on the drain-source voltage. This (nonlinear) parasitic capacitance has to be charged at turn-off of the MOSFET by the drain-source current in rectifier applications that yield input current distortions. A detailed analysis shows that the nonlinear behavior of this capacitance is even more pronounced for modern super junction MOS-FET devices. Whereas C oss increases with increasing chip area, the on-state resistance of the MOSFET decreases accordingly. Hence, a tradeoff between efficiency and input current distortions exists. A detailed analysis of this effect considering different semiconductor technologies is given in this study and a Pareto curve in the η-THD I space is drawn that clearly highlights this relationship. It is further shown that the distortions can be reduced considerably by the application of a proper feedforward control signal counteracting the nonlinear switching delay due to C oss . The theoretical considerations are verified by experimental results taken from 10-kW laboratory prototypes with the switching frequencies of 250 kHz and 1 MHz.Index Terms-Efficiency, high-frequency power converters, input current quality, super junction (SJ).

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Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer

Cited by 19 publications

References 4 publications

Optimized process design flow for fabrication of superjunction VDMOS for enhanced R<inf>DSon</inf>A

Optimized process design flow for fabrication of superjunction VDMOS for enhanced R<inf>DSon</inf>A

Investigation of a Novel High-Permittivity Trench MOS Device with Small Figures of Merit

On the Tradeoff Between Input Current Quality and Efficiency of High Switching Frequency PWM Rectifiers

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