Optimized process design flow for fabrication of superjunction VDMOS for enhanced R<inf>DSon</inf>A

Abstract

In this paper, we proposed a simple and optimized process design flow for the fabrication of Silicon Charge Balance (CB) Super Junction (SJ) Vertical Double Diffused MOS (VD-MOS). Deep Reactive Ion etching (DRI) is used for forming trench p-pillar with process simulation, which reduces the design complexity and number of steps required for device fabrication. The trench p-pillar that has been formed at 1100 • C using DRI causes crystal defects. We remove these defects by annealing at 1150 • C which results in reduction of Area Specific ON Resistance across Source/Drain (S/D) (RDSonA). The proposed process device has Breakdown Voltage (BV) 590V , RDSonA 3.1mΩcm 2 and maximum operating switching frequency (fT )1.027GHz.

A Novel Charge-Protection Superjunction-Insulator VDMOS

“…As we have observed that the SJ-I and SJ devices have bidirectional electric field. To achieve premature BV both electric fields resultant should be equal to E c [14]. Using the above analysis, we have predicted that the proposed SJ-I device achieved higher BV than conventional SJ devices as shown in Fig.…”

Novel strained superjunction VDMOS

“…Here, the observation shows that the higher drive current flow in the s-SJ device as compared to the SJ device for all considered bias conditions due to strain effect. We have developed simple method for the calculation of R on A [7]. In this method, the R on A of the device is the ratio of applied V DS to the resulting J D in the linear region of operation and it is variable with the applied V GS .…”

“…At the top gate oxide thickness of 100 nm is grown by wet oxidation at 900 • C for 125 minutes. Here the gate is formed using poly-Si and S/D ohmic contacts are formed using aluminum metallization [7]. The proposed device unit cell dimension is 5 × 40 µm 2 and the channel length is 1.4 µm.…”

“…The s-SJ VDMOS device performance is analyzed using: on-state characteristics, input capacitance (C in ) effect, gate charge Q g and transient response in comparison with SJ VDMOS. The advantages of proposed s-SJ VDMOS over conventional SJ VDMOS [7,8] are as follows: almost 1∼3 times higher output current carrying capability, less gate charge (Q g ) is required to turn-on the device and high switching speed is possible as compare to conventional SJ VDMOS. This paper is organized as follows: s-SJ VDMOS device specification and advantages are discussed in Section 1.…”

“…Due to this, trade-offs between the breakdown voltage (BV) and area specific on-resistance (R on A) are improved in power devices. Nevertheless, many articles have reported various techniques for improvement of SJ devices in terms of enhancement of BV, optimization in R on A, reduce charge termination (CT), perfect charge-balance (CB) [2,3,4,5,6,7,8,9]. Further, the separate high-K (HK) dielectric pillar in power devices was introduced to avoid impurity inter-diffusion, reduce R on A and improve BV [10,11].…”