Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs

Bashiri, Samira; Aouini, Sadok; Ben-Hamida, Naim; Plett, C.

doi:10.1109/tcsi.2014.2365871

Cited by 14 publications

(7 citation statements)

References 9 publications

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“…The second novel contribution is the low hysteresis of the bang-bang detector. This addresses the problem of the sticky output of the phase detector, resulting in an unstable lock state and increasing limit-cycle jitter [6]. This issue is solved by using a modified phase detector shown in Figure 2 and placing a reset period before every phase detecting period.…”

Section: Phase Detectormentioning

confidence: 99%

A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

Bockel¹,

Prinzie²,

Coa³

et al. 2019

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)

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Section: Phase Detectormentioning

confidence: 99%

A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

Bockel¹,

Prinzie²,

Coa³

et al. 2019

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)

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“…Ideally the output of Phase detector alternates between +1 and -1, i.e. the oscillations are under driven and over driven in every alternate cycle by same amount, thus the average of output frequency will be constant while the phase will be periodically toggling resulting in phase error that in turn generates a limit cycle which has a period two fold that of the reference clock [7].…”

Section: Introductionmentioning

confidence: 99%

Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

Balikai¹,

Kittur²

2019

IJEAT

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A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

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“…On the other hand, most control inputs in industrial or aerospace systems are normally limited by some nonlinear characteristic, such as saturation, dead zone, or backlash‐like hysteresis. As a class of nonlinear inputs, hysteresis widely exists in the aerospace, military, and industrial systems . The nonlinear characteristics of backlash‐like hysteresis could seriously affect tracking performance, and it may cause a severe effect on the whole system .…”

Section: Introductionmentioning

confidence: 99%

Adaptive neural tracking control for nonstrict‐feedback nonlinear systems with unknown backlash‐like hysteresis and unknown control directions

Xin-jun

Yin

et al. 2018

Intl J Robust & Nonlinear

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Summary In this paper, a neural network–based adaptive tracking control problem is investigated for a class of nonstrict‐feedback nonlinear systems in the presence of unknown backlash‐like hysteresis nonlinearity, unmodeled dynamics, and unknown control directions. A state feedback controller is developed for the considered system by applying the adaptive backstepping technique and neural networks. The design difficulties exhibited in this paper due to unmodeled dynamics, unknown control directions, and nonstrict‐feedback form are handled by resorting to a dynamic signal, a Nussbaum function, and the variable separation approach, respectively. It is shown that the designed adaptive controller can guarantee that all the signals remain bounded and that the desired signal can be tracked with a small domain of the origin. A numerical example and an example of a real plant for a one‐link manipulator are provided to show the feasibility of the newly designed controller scheme.

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Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs

Cited by 14 publications

References 9 publications

A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

Adaptive neural tracking control for nonstrict‐feedback nonlinear systems with unknown backlash‐like hysteresis and unknown control directions

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