Modern optical systems increasingly rely on DSP techniques for data transmission at 40Gbs and recently at 100Gbs and above. A significant challenge towards CMOS TX DSP SoC integration is due to requirements for four 6b DACs (Fig. 10.8.1) to operate at 56Gs/s with low power and small footprint. To date, the highest sampling rate of 43Gs/s 6b DAC is reported in SiGe BiCMOS process [1]. CMOS DAC implementations are constraint to 12Gs/s with the output signal frequency limited to 1.5GHz [2][3][4]. This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >30dBc and ENOB>4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die area is less than 0.6×0.4 mm 2 .A critical element in CMOS DAC design at sampling rates Fs = 56Gs/s is a small footprint, so that the clock distribution and data path delays are minimized. In addition, short interconnect guarantees low load capacitance for the driver circuitry and further facilitates die size reduction with speed performance improvement. There are two key obstacles in circuit size reduction: circuit topology with relatively large devices (for an example, poly resistors in CML -style logic) and interconnect metal width. Minimum width is limited by electro-migration (EM) reliability rules. A CMOS logic topology with a minimum DC current in interconnects helps to reduce the EM factor. As a result, 56Gs/s 16:1 MUX circuitry is implemented using a combination of CMOS, pseudo-differential CMOS and transmission gate style of logic. Compactness of the 16:1 MUX design then requires clock phase alignment solution to provide the MUX with precise timing, similar to the phase calibration described in [4].DAC architecture ( Fig. 10.8.2) contains a 256×6b data memory with control register, 16:1 MUX, DAC current-steering matrix, DAC current sources, and finally clock generation and phase alignment block. The memory size provides DAC output data pattern length programmability up to 256b at 56Gs/s; sufficient for time domain 256b PRBS, or frequency domain 256-points FFT testing, such as SFDR and ENOB. The DAC current-steering structure combines two segments: 15 thermometer-encoded MSBs and 2 binary LSBs; there are 17 current sources and current-steering switches in total. Thermometer encoding improves DAC linearity and minimizes output glitch energy [5]. The 4b to 2b split in segmentation provides a balance between circuit complexity and DAC overall performance. There are different techniques to generate the remaining binaryweighted LSBs currents across the on-chip 50Ω load [4,6,7]. Two last solutions prevent the use of series inductive peaking (L1 in Fig. 10.8.2) with 50Ω load at the output. This is why the DAC uses binary-weighted currents of Io/2 and Io/4, where Io is the unary current value. The DAC full scale single-ended output current, FS= 15.75·Io. All 17 currents are generated in the DAC current sources block with 2.5V thick oxide devices. Currents...

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