A 24GS/s 6b ADC in 90nm CMOS

Schván, P.; Bach, J.; Fait, C.; Flemke, P.; Gibbins, Robert; Greshishchev, Y.M.; Ben-Hamida, Naim; Pollex, D.; Sitch, J.E.; Wang, Shing-Chi; Wolczanski, John

doi:10.1109/isscc.2008.4523298

Cited by 83 publications

(23 citation statements)

References 5 publications

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“…A few other very high speed, time interleaved SAR ADCs were described, e.g. [49][50][51]. This certainly defies the argument that a flash ADC is the fastest analog-to-digital conversion architecture.…”

Section: Single and Multi-bit Adc Architecturesmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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Section: Single and Multi-bit Adc Architecturesmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…Today, researchers in industry and academia continue to explore high-speed ADC designs using the traditional fidelity criteria (SFDR and SFDR), where the analog front-end (AFE) in the receiver is designed to behave as a transparent information conduit. In such links, low-power ADCs are particularly difficult to design, and the effective number of bits (ENOB) usually does not exceed six [3], [5], [10]. This paper describes how system-level information can be incorporated into the design of information preserving, high-speed ADCs such that power is dramatically reduced without compromising the bit error-rate (BER) of the overall communication link.…”

Section: System-assisted Mixed-signal (Sams) Designmentioning

confidence: 99%

System-assisted analog mixed-signal design

Shanbhag

Singer

2011

2011 Design, Automation &Amp; Test in Europe

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In this paper, we propose a system-assisted analog mixed-signal (SAMS) design paradigm whereby the mixed-signal components of a system are designed in an application-aware manner in order to minimize power and enhance robustness in nanoscale process technologies. In a SAMS-based communication link, the digital and analog blocks from the output of the information source at the transmitter to the input of the decision device in the receiver are treated as part of the composite channel. This comprehensive systems-level view enables us to compensate for impairments of not just the physical communication channel but also the intervening circuit blocks, most notably the analog/mixed-signal blocks. This is in stark contrast to what is done today, which is to treat the analog components in the transmitter and the analog front-end at the receiver as transparent waveform preservers. The benefits of the proposed system-aware mixed-signal design approach are illustrated in the context of analog-to-digital converters (ADCs) for high-speed links. CAD challenges that arise in designing system-assisted mixed-signal circuits are also described. 1

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“…To exceed 10GS/s, multiple ADCs are time-interleaved using multiple clock phases. By employing a high degree of interleaving, ADC architectures such as pipelined [6][9][10] [11] and successive-approximation (SAR) [12] have been shown to achieve multi-GS/s rates. The only circuit that needs to handle the full data rate is the sample/hold (S/H).…”

Section: A Sampling Rate and Interleavingmentioning

confidence: 99%

“…The sampling speed of each interleaving path is typically a few hundred MHz [12] [19] [21] thus a high degree of interleaving is needed. However, due to the lower input capacitance, up to 24GS/s [12] has been demonstrated using 160-way interleaving. …”

Section: A Adc Architecturementioning

confidence: 99%

ADC-based serial I/O receivers

Yang¹,

Chen²

2009

2009 IEEE Custom Integrated Circuits Conference

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Fully digital receiver frontends have garnered interest for serial I/O receivers. While the speed and resolution are achievable in CMOS technologies, the challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. This paper describes different design techniques and shows that the power can be reduced by constraining the specifications and by making architectural trade-offs.

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A 24GS/s 6b ADC in 90nm CMOS

Cited by 83 publications

References 5 publications

Recent Advances and Trends in High-Performance Embedded Data Converters

Recent Advances and Trends in High-Performance Embedded Data Converters

System-assisted analog mixed-signal design

ADC-based serial I/O receivers

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