ADC-based serial I/O receivers

Yang, Chih-Kong Ken; Chen, E-Hung

doi:10.1109/cicc.2009.5280831

Cited by 9 publications

(2 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As the demand for high data rates increases, receiver front ends that depend on high-speed (multi-GSps) low-resolution ADCs, are being considered for high-speed serial-link communication. This is to fully exploit the benefits of sophisticated digital signal processing techniques [2][3][4]. However, large area and high power consumption of fast ADCs are major concerns.…”

Section: Introductionmentioning

confidence: 99%

A 15.5-mW 20-GSps 4-bit charge-steering flash ADC

Ayesh

Ibrahim

Aboudina

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

This paper presents a 4-bit 20-GSps timeinterleaved flash ADC for an ADC-based high-speed serial-link equalizer. The ADC is designed and simulated in a 65-nm CMOS technology. It dissipates 15.5 mW from a 1-V supply while operating at 20 GSps. Low power consumption is achieved by utilizing charge-steering concept, sharing single reference ladder across all the four interleaved branches, and merging the dynamic latch into the pre-amplifier of the comparator. Results show that for a sinusoidal input frequency of 9.84 GHz with an amplitude of 600 mV dif f , the SNDR of the digital output is 23.9 dB, SFDR is 33.6 dB, and the effective number of bits (ENOB) is 3.67 bits.

show abstract

Section: Introductionmentioning

confidence: 99%

A 15.5-mW 20-GSps 4-bit charge-steering flash ADC

Ayesh

Ibrahim

Aboudina

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

show abstract

“…6 presents FOM versus sampling rate. Knowing that the power budgets per serial I/O link are lower than a few hundred mW, the FOM of the front-end ADC should be lower than 0.5 pJ/conversion-step in order to meet the overall power budgets [20]. Although such level of FOM may not be difficult to achieve for ADCs with low sampling rates, it becomes very challenging to meet when the sampling rate is high (e.g., higher than 10 GS/s) due to clocking costs and high degree of time interleaving.…”

Section: Front-end Adcmentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

show abstract