A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS

Chung, Hayun; Deniz, Zeynep; Rylyakov, Alexander V.; Bulzacchelli, John F.; Friedman, Daniel; Wei, Gu-Yeon

doi:10.1007/s10470-015-0624-x

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…The sampling frequency of each flash ADC is calculated as F s = N/T , where N is the number of interleaving, T is the period of sampling for each Flash core [6]. Hence, it becomes possible to achieve very high sampling rates for time-interleaved ADCs [7,8]. The block diagram of basic time interleaved ADC architecture is depicted in Fig.…”

Section: Introductionmentioning

confidence: 99%

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

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Section: Introductionmentioning

confidence: 99%

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

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A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS

Cited by 2 publications

References 8 publications

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

ADC-Based Backplane Receivers: Motivations, Issues and Future

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