A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

Bockel, Bjorn Van; Prinzie, Jeffrey; Coa, Ying; Leroux, Paul

doi:10.22323/1.343.0027

Cited by 2 publications

(2 citation statements)

References 7 publications

(6 reference statements)

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“…Other TDC topologies use the time interpolation technique. These TDCs include delay line-based TDCs, also known as Tapped Delay Line (TDL) TDCs or Flash TDCs [8,[12][13][14], Vernier delay line TDCs utilized by designers to improve the resolution beyond the cell delay [10,[15][16][17], Delay Locked Loop (DLL) TDC [7,18] or wave union TDC [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

Siecha,

Alemu,

Prinzie

et al. 2023

Electronics

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A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exploits the internal routing resources available in the FPGA as delay elements. A manual placement and routing technique that results in greater resolution and linearity is proposed. The time-interleaving concept is used to improve the resolution of the TDC. A measurement matrix with 512 and 1024 parallel counters is implemented on a Zynq Evaluation and Development (ZED) board. The result of the 1024-unit TDC showed that a dynamic range of 93.6 ns can be measured using a 4-bit coarse gray code counter running at a reference frequency of 171 MHz, and a resolution of 5.7 ps is achieved. The implemented TDC is low-cost, has a fast time to market, and it benefits from the abundant routing resources in the FPGA.

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Section: Introductionmentioning

confidence: 99%

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

Siecha,

Alemu,

Prinzie

et al. 2023

Electronics

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“…With this loop, possible PVT (Process, Voltage and Temperature) variations and variations due to TID are compensated [9]. The PD used in this architecture is the same coming from a previous design [10]. This bang-bang style PD uses an extra reset state inbetween the phase detector states to reduce the hysteresis, which results in a smaller output jitter of the DLL.…”

Section: Introductionmentioning

confidence: 99%

Design of a 4 ps radiation hardened TDC with an improved interpolation technique

Bockel¹,

Prinzie²,

Leroux³

2020

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2019)

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This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations-and variations due to ionizing radiation.

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A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

Cited by 2 publications

References 7 publications

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

Design of a 4 ps radiation hardened TDC with an improved interpolation technique

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