5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

Abstract

A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exploits the internal routing resources available in the FPGA as delay elements. A manual placement and routing technique that results in greater resolution and linearity is proposed. The time-interleaving concept is used to improve the resolution of the TDC. A measurement matrix with 512 and 1024 parallel counters is implemented on a Zynq Evaluation and Development (ZED) board. The result of the 1024-unit TDC showed that a dynamic range of 93.6 ns can be measured using a 4-bit coarse gray code counter running at a reference frequency of 171 MHz, and a resolution of 5.7 ps is achieved. The implemented TDC is low-cost, has a fast time to market, and it benefits from the abundant routing resources in the FPGA.

High-Performance Wave Union Time-to-Digital Converter Implementation Based on Routing Path Delays of FPGA

“…The LUTs were manually positioned in a slice near where the source of the hit signal is located. Our TDC designed and built using a matrix of 1024 counters, with the routing paths serving as delay components [14]. The triggering signal that controls the pulse train's creation and propagation is called the enable signal (EN).…”

“…The architecture of the WU-A TDC is depicted in Figure 2. Our designed WU-A launcher sets up two 1-0 and one 0-1 transi- Our TDC designed and built using a matrix of 1024 counters, with the routing paths serving as delay components [14]. The triggering signal that controls the pulse train's creation and propagation is called the enable signal (EN).…”

“…By using the DSP blocks as delay elements, a 4.2 ps resolution could be achieved, but the differential non-linearity is limited to 20 least significant bits [11]. FPGA routing wires can be utilized as delay components in the construction of reliable TDCs because of their tolerance to PVT (process, voltage, and temperature) variations [12][13][14].…”

“…In our previous work [14], we built a 5.7 ps resolution TDC based on a 1024 matrix of counters on the XC7Z020-CLG484 xilinx seven-series FPGA, placing the counters in an 8 × 128 rectangular matrix and combining short and long routing wires to improve the resolution and linearity. Even without calibration, the implemented TDC exhibits a differential non-linearity (RMS) of 0.43 LSB and an integral non-linearity (RMS) of 2.15 LSB.…”

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

“…In [8], the authors utilize two distinct manual placement and routing approaches to enhance precision of FPGA-based TDCs. In the first approach, uniform routing paths and controlled delay elements are used while the second approach enhances the first by introducing a combination of long and short routing wires.…”