Analysis and Modeling of One-Dimensional Folded Vertical Hall Sensor With Readout Circuit

Sung, Guo-Ming; Wang, Weiyu; Yu, Chih-Ping

doi:10.1109/jsen.2017.2754295

Cited by 10 publications

(8 citation statements)

References 23 publications

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“…To name a few, it includes developing models of memristor [23], ferroelectric transistors [24], thermoelectric module [25]. SPICE simulation of magnetic field sensors is covered in the following publications: Physical simulations of response time in Hall sensor devices [26], Behavioral model of magnetic sensors for SPICE simulations [27], Analysis and Modeling of One-Dimensional Folded Vertical Hall Sensor with Readout Circuit [28].…”

Section: Literature Overviewmentioning

confidence: 99%

Structure and 3-D Model of a Solid State Thin-Film Magnetic Sensor

Barylo

Holyaka

Marusenkova

et al. 2021

Phys. Chem. Solid St.

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Vector 3-D magnetic sensors form the basis of measurement devices for magnetic field mapping and magnetic tracking. Typically, such sensors utilize specific constructions based on split Hall structures (SHS). An SHS-based 3-D magnetic sensor is a bulk semiconductor integrated structure with 8 or more contacts. Combining current flow directions through the contacts and measuring the corresponding voltages, one defines projections BX, BY, BZ of the magnetic field vector. This work presents a novel design of 3-D solid state magnetic sensors that requires no insulation by p-n junctions and can be implemented by thin-film technology traditionally used for fabrication of Hall sensors including those based on InSb films. Besides, a SPICE model of the 3-D magnetic sensor is provided, which helps design the proposed sensor and refine techniques of its calibration.

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Section: Literature Overviewmentioning

confidence: 99%

Structure and 3-D Model of a Solid State Thin-Film Magnetic Sensor

Barylo

Holyaka

Marusenkova

et al. 2021

Phys. Chem. Solid St.

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“…As different sensors have different output ranges, as discussed in [5], a typically measured thermocouple voltage is 0-3 mV from 15 ℃ to 90 ℃. ±15 mV with the dc magnetic set form −15 to 15 mT as discussed in [6]. Herein, a VGM was used in the CSIA to configure different input ranges and improve the ROIC's application.…”

Section: Design Of Vgm and Cmos Buffer Amplifiermentioning

confidence: 99%

“…In recent years, multiple sensors integrated onto the same chip have become a new trend in sensor development [4]. Most sensors, such as thermocouples, thermopile infrared (IR) sensors, and bridge transducers (Hall sensors and resistive Wheatstone bridge sensors), typically have a low-frequency output and small DC voltage signals of the millivolt-level [5][6][7]. Therefore, precision amplifiers are required to boost such small signals to levels that are compatible with the input ranges typical of the analog-to-digital converters of the read-out IC (ROIC).…”

Section: Introductionmentioning

confidence: 99%

A low power read-out integrated circuit for multiple sensors

Huang

Wei

Wang

et al. 2020

IEICE Electron. Express

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This paper proposes a low power read-out integrated circuit (ROIC) for multiple sensors having a DC output signal. It comprises a chopper-stabilized instrumentation amplifier (CSIA) followed by a second-order incremental analog-to-digital converter (IADC). The CSIA has a dual-frequency path to effectively eliminate any 1/f noise and offset. A variable gain module (VGM) is also connected to the CSIA to improve its range of potential applications. A CMOS buffer amplifier followed by the CSIA is used to achieve the ROIC's linearity and drive capability. The back-end of the ROIC has a switchedcapacitor IADC to provide a digital output. The correlated double sampling (CDS) technique was used in the IADC's first integrator to reduce the offset and noise. The combination of these techniques enables the ROIC to achieve an input referred offset of 5 μV and a best error voltage of ±0.01 mV. The ROIC was implemented in 0.18 μm CMOS technology. It occupies an area of approximately 2.56 mm2 and consumes 835 μA of current from a 1.6 V of supply voltage.

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“…However, it will inevitably increase the additional fabrication cost. Moreover, offset is quite difficult to get rid of it on VHDs due to the lack of electrical symmetry structure such as traditional five-contact devices [14] . The offset voltage is often much larger than the Hall voltage, making it difficult for VHDs to detect low magnetic fields.…”

Section: Introductionmentioning

confidence: 99%

An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

Shu¹,

Jiang²,

Hu³

et al. 2022

J. Semicond.

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An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measurement. To improve the magnetic sensitivity and to obtain low offset, a fully symmetric vertical Hall device (FSVHD) has been optimized with a minimum size design. A new four-phase spinning current modulation associated with a correlated double sampling (CDS) demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage. The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occupies an area of 1.54 mm2. The experimental results show in the magnetic field range from –200 to 200 mT, the entire vertical Hall sensor performs with the linearity of 99.9% and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT. Meanwhile, it consumes 4.5 mW at a 3.3 V supply voltage. The proposed vertical Hall sensor is very suitable for the low-cost system-on-chip (SOC) implementation of 2D or 3D magnetic microsystems.

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Analysis and Modeling of One-Dimensional Folded Vertical Hall Sensor With Readout Circuit

Cited by 10 publications

References 23 publications

Structure and 3-D Model of a Solid State Thin-Film Magnetic Sensor

Structure and 3-D Model of a Solid State Thin-Film Magnetic Sensor

A low power read-out integrated circuit for multiple sensors

An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

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