Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units

Olivieri, Mauro; Pappalardo, F.; Smorfa, Simone; Visalli, Giuseppe

doi:10.1109/tcsii.2007.896937

Cited by 8 publications

(1 citation statement)

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“…The architecture here described utilizes LUTs more efficiently than previous designs demonstrated in [11]- [12] and exhibits significantly reduced hardware resources requirement, power consumption and computational delay. This is a graceful result, given that, as a part of the critical computational path, the LZC can contribute up to 30% to the worst-case delay of a floatingpoint unit [13] and up to 15% to the resources utilization [14].…”

Section: Introductionmentioning

confidence: 99%

Design of Leading Zero Counters on FPGAs

Perri

Spagnolo

Frustaci

et al. 2023

IEEE Embedded Syst. Lett.

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This letter presents a novel leading zero counter (LZC) able to efficiently exploits the hardware resources available within state-of-the-art FPGA devices to achieve high speed performances with limited energy consumption. Postimplementation results, obtained for operands bit-widths varying between 4-and 64-bit, demonstrate that the new design improves its direct competitors in terms of occupied lookup tables (LUTs), power consumption and computational speed. As an example, when implemented using the Xilinx Artix-7 xc7a100tcsg324 device, the new 64-bit LZC utilizes up to 36% less LUTs, dissipates up to 2.8 times lower power and is up to 20% faster than state-ofthe-art counterparts.

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Section: Introductionmentioning

confidence: 99%