Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC

Liu, Shaoteng; Jantsch, Axel; Lu, Zhonghai

doi:10.1109/dsd.2013.13

Cited by 16 publications

(9 citation statements)

References 27 publications

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“…in the case of a multimedia application relaying a stream of video or audio data at a fixed bitrate. In [6], Liu shows after a detailed analysis that CS networks will outperform PS NoCs for packet size exceeding 30 flits/packet under low load and 60-70 flits/packet under high network load.…”

Section: Introductionmentioning

confidence: 99%

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Costs and benefits of flexibility in spatial division circuit switched networks-on-chip

Ejaz

Jantsch

2013

Proceedings of the Sixth International Workshop on Network on Chip Architectures

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Although most Network-on-Chip (NoC) designs are based on Packet Switching (PS), the importance of Circuit Switching (CS) should not be underestimated. Many MPSoC executing real-time applications require an underlying communication backbone that can relay messages from one node to another with guaranteed throughput. Compared to PS, CS can provide guaranteed throughput with lower area and power overheads. It is also highly suited for applications where nodes transfer long messages. Spatial Division Multiplexing (SDM) can allow more efficient use of available network resources by dividing them among multiple simultaneous transactions. The network developed by Vali [1] has three design variations based on the number of sub-channels, has a predictable connection setup time, and uses CS to provide guaranteed throughput once a connection is established. In this paper we use this network as a basis to study the effect of flexibility based on SDM, on the performance of a CS networks. A network evaluation platform has been developed to configure and evaluate networks with a maximum of 8 sub-networks, with each subnetwork comprising of 1, 2 or 4 sub-channels. We show that under uniform traffic pattern with requests of uniform random bandwidth (BW) requirement, a less flexible network outperforms a network with higher flexibility due to a phenomenon we call 'stray requests'. We conclude this paper by showing that under high network traffic, performance of our flexible networks can be as much as 113% better than HAGAR [2] and Liu's [3] network.

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Section: Introductionmentioning

confidence: 99%

“…Such characteristics of a PS NoC make its use unappealing in an area and power constrained environment [6,10]. On the other hand, flits travelling on a reserved path in a CS network do not face any contention leading to a simplified and energy efficient design.…”

Section: Introductionmentioning

confidence: 99%

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip

Ejaz

Jantsch

2013

Proceedings of the Sixth International Workshop on Network on Chip Architectures

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“…packet rate, packet size, buffer size, routing algorithm) on the performance of SoC. Liu et al [31] drew a comparison between circuit switched NoC and Packet Switched NoC. In real-life applications, almost most of parameters (i.e.…”

Section: Reconfigurable Parameters Of Nocmentioning

confidence: 99%

“…Currently, such flexibility can be provided by a large packet-switched NoC with an over-engineered total bandwidth. Unfortunately, such a NoC would result in a significant area overhead because only a fraction of its bandwidth is really utilized for a given application ( [17,30,31]). Another way is the reconfigurable NoC that enhanced the dynamical reconfigurability of the SoC platform; therefore, this also results in the further reduction in area and power consumption of the design ( [17,30]).…”

Section: Evolution Of System-on-chipsmentioning

confidence: 99%

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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“…The packet based network can outperform circuit based network at high injection rate, if the packet size is less than 62 flits [38]. Therefore, we assumed the packet payload of 20 flits.…”

Section: Noc-based Test Platformmentioning

confidence: 99%

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

Ansari¹,

Kim²,

Jung³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

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Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC

Cited by 16 publications

References 27 publications

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip

A Survey on Reconfigurable System-on-Chips

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

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