Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit

Abstract

In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodologies for FFs analysis and design reported in Part I. In particular, the analysis accounts for the impact of leakage and layout parasitics on the optimization of the circuits. The tradeoffs between leakage, area, clock load, delay, and other interesting properties are extensively discussed. The investigation permits to derive several considerations on each FF class and to identify the best topologies for a targeted application.

Design and Analysis of Dual Edge Triggered (DET) Flip-Flops Using Multiple C-Elements

“…Post-layout simulations showed that the kit's estimates for small designs are often conservative and that compact circuits often perform slightly faster in post-layout simulations than in schematic simulations with the automatic parasitic network estimation turned on. The simulation test bench that is used in this comparison is very similar to the ones used in [5], [13], [14]. The Q output of a simulated flip-flop is connected to a load of four symmetric inverters with their n-type transistors sized at minimum recommended width.…”

Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor

“…The charge keeper circuit for the internal node can be saved due to the addition of pull-up pMOS transistor. With the circuit simplicity, this approach also keep down the load capacitance of node X [14], [15].…”

Design of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme

“…Accordingly, Clock-gated FFs are unsuitable for nanometer technologies. Among [3] DET FFs, the DET-TGLM represents the most energy-efficient solution in the deep low-energy region, together with TGFF. It is the DET counterpart of TGFF and they show similar performances since the greater layout complexity of DET-TGLM is compensated by the energy reduction due to the DET property.…”

“…It has longer data to Q delay compared to CDFF. Since three stacked transistor is used it faces worst case delay [3]. To overcome this delay a pull down circuitry is used but the disadvantage is that extra layout area and power consumption.…”

“…If the sampling of the input is performed in both rising and falling edge of clock (Double-Edge triggered) [3], the frequency of the clock can be half of the clock frequency of the single edge triggered FF called Double-edge triggered Flip-Flop. Double-edge triggered Flip-Flop (DETFF) has less dynamic power consumption, static power, and delay compared to the previous flip-flops.…”