Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

Bertrand, Géraldine; Delage, C.; Bafleur, Marise; Nolhier, Nicolas; Dorkel, Jean-Marie; Nguyen, Quang Van; Mauran, Nicolas; Trémouilles, David; Perdu, Philippe

doi:10.1109/4.944666

Cited by 33 publications

(3 citation statements)

References 13 publications

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“…The electrostatic discharge (ESD) reliability is an important issue for high-voltage MOSFET with applications in these products. In smart-power technology, most of the publications related to ESD protection devices concern the lateral or vertical bipolar transistors [1], [2]. However, process complexity and fabrication cost are increased by adding bipolar modules into the CMOS process.…”

Section: Introductionmentioning

confidence: 99%

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

Ker

Lin

2004

IEEE Electron Device Lett.

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The double snapback characteristic in the highvoltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.Index Terms-Double-diffused drain (DDD), electrostatic discharge (ESD), high-voltage nMOSFET, lateral diffused MOS (LDMOS), latchup.

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Section: Introductionmentioning

confidence: 99%

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

Ker

Lin

2004

IEEE Electron Device Lett.

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“…Typical protection structures are based on self-biased NPN bipolar transistors given their good ESD robustness. The main drawback of the NPN transistor is its strong snapback behavior [3][4][5], that requires stacking several structures to increase the clamping voltage above the power supply value and then fulfill the requirement of latch-up free operation [6]. To avoid stacking structures, which is detrimental to both silicon area and on-state resistance, a solution consists in controlling this strong snapback effect (mostly design approach [7]) or using reduced gain PNP bipolar transistors that do not exhibit this effect [8,9].…”

Section: Introductionmentioning

confidence: 99%

Analytical description of the injection ratio of self-biased bipolar transistors under the very high injection conditions of ESD events

Gendron¹,

Renaud²,

Bafleur³

et al. 2008

Solid-State Electronics

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This paper proposes a 1D-analytical description of the injection ratio of a self-biased bipolar transistor under very high current injection conditions. Starting from an expression of the current gain based on the stored charge into the emitter and base regions, we derive a new analytical expression of the current injection ratio. This analytical description demonstrates the presence of an asymptotic limit for the injection ratio at very high current densities, as the ratio of electron/hole mobilities in the case of an NPN transistor and to the ratio of hole/electron saturation velocities for a PNP. Moreover, for the first time, a base narrowing effect is demonstrated and explained in the case of a self-biased PNP, in contrast with the base widening effect (Kirk effect [Kirk CT, A theory of transistor cutoff frequency (fT) falloff at high current densities, IRE Trans Electr Dev 1961: p. 164-73]) reported for lower current density. These results are validated by numerical simulation and show a good agreement with experimental characterizations of transistors especially designed to operate under extreme condition such as electrostatic discharge (ESD) events.

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“…In smart-power technology, an HV MOSFET, siliconcontrolled rectifier (SCR) device, and bipolar junction transistor were used as on-chip electrostatic discharge (ESD) protection devices [1]- [7]. Some ESD protection designs used the lateral or vertical bipolar transistors as ESD protection devices in smart-power technology [5], [6]. However, fabrication cost and process complexity are increased by adding bipolar modules into the CMOS process.…”

Section: Introductionmentioning

confidence: 99%

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

Ker

Chang

2007

IEEE Trans. Device Mater. Relib.

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A new electrostatic discharge (ESD) protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-linepulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5-µm high-voltage complementary MOS process. Such ESDenhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 µm, the machine-model ESD levels of the HVPSCR are as high as 1100, 1300, and 1900 V, respectively. Index Terms-Electrostatic discharge (ESD), high-voltage p-type silicon-controlled rectifier (HVPSCR), human body model (HBM), machine model (MM), secondary breakdown current (It2), vacuum fluorescent display (VFD).

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Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

Cited by 33 publications

References 13 publications

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

Analytical description of the injection ratio of self-biased bipolar transistors under the very high injection conditions of ESD events

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

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