Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

Abstract

The double snapback characteristic in the highvoltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.Index Terms-Double-diffused drain (DDD), electrostatic discharge (ESD), high-voltage nMOSFET, lateral diffused MOS (LDMOS), latchup.

Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device

“…Upon the triggering of parasitic bipolar junction transistor (BJT) operation, a vertical directional U-shaped current path is formed between the drain N+ diffusion and the source N+ diffusion region. This is the situation in the 1st on-state, both in the EDNMOS with low BDC and in the EDNMOS with high BDC, before the characteristic double snapback occurs [8].…”

“…The low resistive and short current path following the deep electron channel can explain the occurrence of the 2nd on-state with such a low on-resistance. The high electron injection induced base push-out and the consequential double snapback has been addressed in several publications [8][9][10].…”

“…Recently, the high voltage operating double N-type MOSFET devices are shown to have double snapback phenomenon, where the 2nd on-state is characterized by extremely low snapback holding voltage [8]. Related mechanism is known to be the high electron injection induced base push-out [9,10].…”

Analytical description of the injection ratio of self-biased bipolar transistors under the very high injection conditions of ESD events

“…Typical protection structures are based on self-biased NPN bipolar transistors given their good ESD robustness. The main drawback of the NPN transistor is its strong snapback behavior [3][4][5], that requires stacking several structures to increase the clamping voltage above the power supply value and then fulfill the requirement of latch-up free operation [6]. To avoid stacking structures, which is detrimental to both silicon area and on-state resistance, a solution consists in controlling this strong snapback effect (mostly design approach [7]) or using reduced gain PNP bipolar transistors that do not exhibit this effect [8,9].…”

“…However, during the very short duration of an ESD event, protection devices can briefly sustain current densities as high as 10 6 A cm À2 without destruction. Since the current peak lasts only for a few hundreds of nanoseconds, the heat generation in the protection device may not be sufficient to induce a melting of the silicon, and to damage the structure.…”