A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good R ON capabilities (~1Ω). The protection of high voltage I/Os with a narrow ESD design window ranging from 80V to 100V can be implemented in a reduced surface of 151*140 µm 2 , which represents a state-of-the-art breakthrough.
This paper proposes a 1D-analytical description of the injection ratio of a self-biased bipolar transistor under very high current injection conditions. Starting from an expression of the current gain based on the stored charge into the emitter and base regions, we derive a new analytical expression of the current injection ratio. This analytical description demonstrates the presence of an asymptotic limit for the injection ratio at very high current densities, as the ratio of electron/hole mobilities in the case of an NPN transistor and to the ratio of hole/electron saturation velocities for a PNP. Moreover, for the first time, a base narrowing effect is demonstrated and explained in the case of a self-biased PNP, in contrast with the base widening effect (Kirk effect [Kirk CT, A theory of transistor cutoff frequency (fT) falloff at high current densities, IRE Trans Electr Dev 1961: p. 164-73]) reported for lower current density. These results are validated by numerical simulation and show a good agreement with experimental characterizations of transistors especially designed to operate under extreme condition such as electrostatic discharge (ESD) events.
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